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PIC16C8X
8-Bit CMOS EEPROM Microcontrollers
Devices Included in this Data Sheet * * * * * * PIC16C83 PIC16CR83 PIC16C84 PIC16C84A PIC16CR84 Extended voltage range devices available (PIC16LC8X)
Pin Diagram
PDIP, SOIC
RA2 RA3 RA4/T0CKI MCLR VSS RB0/INT RB1 RB2 RB3
*1 2 3 4 5 6 7 8 9
18 17 16 15 14 13 12 11 10
RA1 RA0 OSC1/CLKIN OSC2/CLKOUT VDD RB7 RB6 RB5 RB4
PIC16C8X
High Performance RISC CPU Features
* Only 35 single word instructions to learn * All instructions single cycle (400 ns @ 10 MHz) except for program branches which are two-cycle * Operating speed: DC - 10 MHz clock input DC - 400 ns instruction cycle
Memory Device Program RAM Data EEPROM 64 64 64 64 64 10 MHz 10 MHz 10 MHz 10 MHz 10 MHz Freq Max.
Special Microcontroller Features
* * * * * * * * Power-on Reset (POR) Power-up Timer (PWRT) Oscillator Start-up Timer (OST) Watchdog Timer (WDT) with its own on-chip RC oscillator for reliable operation Code-protection Power saving SLEEP mode Selectable oscillator options Serial In-System Programming - via two pins (ROM devices support only Data EEPROM programming)
PIC16C83 512 words 36 PIC16CR83 512 words 36 PIC16C84 1 K-words 36 PIC16C84A 1 K-words 68 PIC16CR84 1 K-words 68 ROM Program Memory Devices
* * * * * *
14-bit wide instructions 8-bit wide data path 15 special function hardware registers Eight-level deep hardware stack Direct, indirect and relative addressing modes Four interrupt sources: - External RB0/INT pin - TMR0 timer overflow - PORTB<7:4> interrupt on change - Data EEPROM write complete * 1,000,000 data memory EEPROM ERASE/WRITE cycles - Typical * EEPROM Data Retention > 40 years
CMOS Technology
* Low-power, high-speed CMOS EEPROM technology * Fully static design * Wide operating voltage range: - Commercial: 2.0V to 6.0V - Industrial: 2.0V to 6.0V * Low power consumption: - < 2 mA typical @ 5V, 4 MHz - 15 A typical @ 2V, 32 kHz - < 1 A typical standby current @ 2V (all devices except PIC16C84)
Peripheral Features
* 13 I/O pins with individual direction control * High current sink/source for direct LED drive - 25 mA sink max. per pin - 20 mA source max. per pin * TMR0: 8-bit timer/counter with 8-bit programmable prescaler
(c) 1995 Microchip Technology Inc.
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PIC16C8X
Table of Contents 1.0 General Description................................................................................................................................................3 2.0 PIC16C8X Device Varieties ....................................................................................................................................5 3.0 Architectural Overview............................................................................................................................................7 4.0 Memory Organization ...........................................................................................................................................11 5.0 I/O Ports................................................................................................................................................................21 6.0 Timer0 Module and TMR0 Register......................................................................................................................27 7.0 Data EEPROM Memory .......................................................................................................................................33 8.0 Special Features of the CPU ................................................................................................................................37 9.0 Instruction Set Summary ......................................................................................................................................53 10.0 Development Support ...........................................................................................................................................65 11.0 Electrical Characteristics for PIC16C84................................................................................................................71 12.0 DC & AC Characteristics Graphs/Tables for PIC16C84........................................................................................81 13.0 Electrical Characteristics for PIC16C83, PIC16CR83, PIC16C84A and PIC16CR84 ..........................................95 14.0 DC & AC Characteristics Graphs/Tables for PIC16C83, PIC16CR83, PIC16C84A, and PIC16CR84 ...............107 15.0 Packaging Information ........................................................................................................................................109 Appendix A: Changes ...............................................................................................................................................113 Appendix B: Compatibility.........................................................................................................................................113 Appendix C: What's New ..........................................................................................................................................114 Appendix D: What's Changed...................................................................................................................................114 Appendix E: PIC16C84 Conversion Considerations.................................................................................................115 Appendix F: PIC16/17 Microcontrollers ....................................................................................................................117 Index.....................................................................................................................................................125 Connecting to Microchip BBS ..............................................................................................................129 Reader Response ................................................................................................................................130
To Our Valued Customers
We constantly strive to improve the quality of all our products and documentation. We have spent an exceptional amount of time to ensure that these documents are correct. However, we realize that we may have missed a few things. If you find any information that is missing or appears in error, please use the reader response form in the back of this data sheet to inform us. We appreciate your assistance in making this a better document. To assist you in the use of this document, Appendix C contains a list of new information in this data sheet, while Appendix D contains information that has changed
DS30081F-page 2
(c) 1995 Microchip Technology Inc.
PIC16C8X
1.0 GENERAL DESCRIPTION
The PIC16C8X is a group in the PIC16CXX family of low-cost, high-performance, CMOS, fully-static, 8-bit microcontrollers. This group contains the following devices: * * * * * PIC16C83 PIC16CR83 PIC16C84 PIC16C84A PIC16CR84 The devices with EEPROM program memory allows the same device package to be used for prototyping and production. In-circuit reprogrammability allows the code to be updated without the device being removed from the end application. This is useful in the development of many applications where the device may not be easily accessible, but the prototypes may require code updates. This is also useful for remote applications where the code may need to be updated (such as rate information). Table 1-1 lists the features of the PIC16C8X, and Appendix F: list the features of all of the Microchip microcontrollers. A simplified block diagram of the PIC16C8X is shown in Figure 3-1. The PIC16C8X fits perfectly in applications ranging from high speed automotive and appliance motor control to low-power remote sensors, electronic locks, security devices and smart cards. The EEPROM technology makes customization of application programs (transmitter codes, motor speeds, receiver frequencies, security codes, etc.) extremely fast and convenient. The small footprint packages make this microcontroller series perfect for all applications with space limitations. Low-cost, low-power, high performance, ease of use and I/O flexibility make the PIC16C8X very versatile even in areas where no microcontroller use has been considered before (e.g., timer functions, serial communication, capture and compare, PWM functions and co-processor applications). The serial in-system programming feature (via two pins) offers flexibility of customizing the product after complete assembly and testing. This feature can be used to serialize a product, store calibration data, or program the device with the current firmware before shipping.
All PIC16/17 microcontrollers employ an advanced RISC architecture. PIC16CXX devices have enhanced core features, eight-level deep stack, and multiple internal and external interrupt sources. The separate instruction and data buses of the Harvard architecture allow a 14-bit wide instruction word with a separate 8-bit wide data bus. The two stage instruction pipeline allows all instructions to execute in a single cycle, except for program branches (which require two cycles). A total of 35 instructions (reduced instruction set) are available. Additionally, a large register set gives some of the architectural innovations used to achieve a very high performance. PIC16C8X microcontrollers typically achieve a 2:1 code compression and up to a 2:1 speed improvement (at 10 MHz) over other 8-bit microcontrollers in their class. The PIC16C8X has up to 68 bytes of RAM, 64 bytes of Data EEPROM memory, and 13 I/O pins. A timer/counter is also available. The PIC16CXX family has special features to reduce external components, thus reducing cost, enhancing system reliability and reducing power consumption. There are four oscillator options, of which the single pin RC oscillator provides a low-cost solution, the LP oscillator minimizes power consumption, XT is a standard crystal, and the HS is for High Speed crystals. The SLEEP (power-down) mode offers power saving. The user can wake the chip from sleep through several external and internal interrupts and resets. A highly reliable Watchdog Timer with its own on-chip RC oscillator provides protection against software lock-up.
1.1
Family and Upward Compatibility
Those users familiar with the PIC16C5X family of microcontrollers will realize that this is an enhanced version of the PIC16C5X architecture. Please refer to Appendix A for a detailed list of enhancements. Code written for PIC16C5X can be easily ported to the PIC16C8X (Appendix B).
1.2
Development Support
The PIC16CXX family is supported by a full-featured macro assembler, a software simulator, an in-circuit emulator, a low-cost development programmer and a full-featured programmer. A "C" compiler and fuzzy logic support tools are also available.
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TABLE 1-1: PIC16C8X FAMILIES OF DEVICES
Clock
n (M ) Hz
Memory
em o ry
Peripherals
Features
M
E
D
D
In
I/O
a
xim
RO
M
Ti
TMR0 TMR0 TMR0 TMR0 TMR0
m
Pi
um
R EP
a at
M
a at
er
r te
ru
ns
e Fr
qu
e
y nc
of
O
p
a er
tio
o Pr
gr
am
M
O
M
em
or
y
(
t by
es
)
EE
O PR
M
(b
yt
es
)
u od le ( s)
S pt ou rc es
M
V
ta ol
ge
R
an
ge
(V
ol
ts
)
P
k ac
ag
es
PIC16C83(1) PIC16CR83(1) PIC16C84 PIC16C84A(1) PIC16CR84(1)
10 10 10 10 10
512 -- 1K 1K --
-- 512 -- -- 1K
36 36 36 68 68
64 64 64 64 64
4 4 4 4 4
13 13 13 13 13
2.0-6.0 18-pin DIP, SOIC 2.0-6.0 18-pin DIP, SOIC 2.0-6.0 18-pin DIP, SOIC 2.0-6.0 18-pin DIP, SOIC 2.0-6.0 18-pin DIP, SOIC
Notes: - All PIC16/17 family devices have Power-on Reset, selectable Watchdog Timer, selectable code protect, and high I/O current capability. - All PIC16CXX family devices use serial programming with clock pin RB6 and data pin RB7. 1: Please contact your local sales office for availability of these devices.
DS30081F-page 4
(c) 1995 Microchip Technology Inc.
PIC16C8X
2.0 PIC16C8X DEVICE VARIETIES
2.2
A variety of frequency ranges and packaging options are available. Depending on application and production requirements the proper device option can be selected using the information in this section. When placing orders, please use the "PIC16C8X Product Identification System" at the back of this data sheet to specify the correct part number. There are four device "types" as indicated in the device number. 1. C, as in PIC16C84. These devices have EEPROM program memory and operate over the standard voltage range. LC, as in PIC16LC84. These devices have EEPROM program memory and operate over an extended voltage range. CR, as in PIC16CR83. These devices have ROM program memory and operate over the standard voltage range. LCR, as in PIC16LCR84. These devices have ROM program memory and operate over an extended voltage range.
Quick-Turnaround-Production (QTP) Devices
Microchip offers a QTP Programming Service for factory production orders. This service is made available for users who choose not to program a medium to high quantity of units and whose code patterns have stabilized. The devices have all EEPROM locations and configuration options already programmed by the factory. Certain code and prototype verification procedures do apply before production shipments are available. For information on submitting a QTP code, please contact your Microchip Regional Sales Office.
2.
2.3
Serialized Quick-TurnaroundProduction (SQTP SM ) Devices
3.
4.
Microchip offers the unique programming service where a few user-defined locations in each device are programmed with different serial numbers. The serial numbers may be random, pseudo-random or sequential. Serial programming allows each device to have a unique number which can serve as an entry-code, password or ID number. For information on submitting a SQTP code, please contact your Microchip Regional Sales Office.
When discussing memory maps and other architectural features, the use of C (CR) also implies the LC (LCR) versions.
2.1
Electrically Erasable Devices
These devices are offered in the lower cost plastic package, even though the device can be erased and reprogrammed. This allows the same device to be used for prototype development and pilot programs as well as production. A further advantage of the electrically erasable version is that they can be erased and reprogrammed in-circuit, or by device programmers, such as Microchip's PICSTARTTM or PRO MATETM programmers.
2.4
ROM Devices
Some of Microchip's devices have a corresponding device where the program memory is a ROM. These devices give a cost savings over Microchip's traditional user programmed devices (EPROM, EEPROM). ROM devices (PIC16CR8X) do not allow serialization information in the program memory space. The user may program this information into the Data EEPROM. For information on submitting a ROM code, please contact your Microchip Regional Sales Office.
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NOTES:
DS30081F-page 6
(c) 1995 Microchip Technology Inc.
PIC16C8X
3.0 ARCHITECTURAL OVERVIEW
The high performance of the PIC16CXX family can be attributed to a number of architectural features commonly found in RISC microprocessors. To begin with, the PIC16CXX uses a Harvard architecture. This architecture has the program and data are accessed from separate memories. So the device has a program memory bus and a data memory bus. This improves bandwidth over traditional von Neumann architecture where program and data are fetched from the same memory (accesses over the same bus). Separating program and data memory further allows instructions to be sized differently than the 8-bit wide data word. PIC16C8X opcodes are 14-bits wide, enabling single word instructions. The full 14-bit wide program memory bus fetches a 14-bit instruction in a single cycle. A two-stage pipeline overlaps fetch and execution of instructions (Example 3-1). Consequently, all instructions execute in a single cycle (400 ns @ 10 MHz) except for program branches. The PIC16C83 and PIC16CR83 address 512 x 14 of program memory, and the PIC16C84, PIC16C84A, and PIC16CR84 address 1K x 14 program memory. All program memory is internal. The PIC16CXX can directly or indirectly address its register files or data memory. All special function registers including the program counter are mapped in the data memory. An orthogonal (symmetrical) instruction set that makes it possible to carry out any operation on any register using any addressing mode. This symmetrical nature and lack of `special optimal situations' make programming with the PIC16CXX simple yet efficient. In addition, the learning curve is reduced significantly. PIC16CXX devices contain an 8-bit ALU and working register. The ALU is a general purpose arithmetic unit. It performs arithmetic and Boolean functions between data in the working register and any register file. The ALU is 8-bits wide and capable of addition, subtraction, shift and logical operations. Unless otherwise mentioned, arithmetic operations are two's complement in nature. In two-operand instructions, typically one operand is the working register (W register), and the other operand is a file register or an immediate constant. In single operand instructions, the operand is either the W register or a file register. The W register is an 8-bit working register used for ALU operations. It is not an addressable register. Depending on the instruction executed, the ALU may affect the values of the Carry (C), Digit Carry (DC), and Zero (Z) bits in the STATUS register. The C and DC bits operate as a borrow and digit borrow out bit, respectively, in subtraction. See the SUBLW and SUBWF instructions for examples. A simplified block diagram for the PIC16C8X is shown in Figure 3-1, its corresponding pin description is shown in Table 3-1.
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FIGURE 3-1: PIC16C8X BLOCK DIAGRAM
13 EEPROM/ROM Program Memory PIC16C83/R83 512 x 14 PIC16C84/84A/R84 1K x 14 Program Bus 14 Instruction reg 5 Direct Addr Program Counter Data Bus 8 EEPROM Data Memory RAM File Registers PIC16C83/R83/84 36 x 8 PIC16C84A/R84 68 x 8 7 RAM Addr
8 Level Stack (13-bit)
EEDATA
EEPROM Data Memory 64 x 8
EEADR
Addr Mux 7 Indirect Addr TMR0
FSR reg RA4/T0CKI STATUS reg 8
Power-up Timer Instruction Decode & Control Oscillator Start-up Timer Power-on Reset Watchdog Timer W reg ALU
MUX I/O Ports
RA3:RA0 RB7:RB1
Timing Generation
RB0/INT
OSC2/CLKOUT OSC1/CLKIN
MCLR
VDD, VSS
DS30081F-page 8
(c) 1995 Microchip Technology Inc.
PIC16C8X
TABLE 3-1:
Pin Name OSC1/CLKIN OSC2/CLKOUT
PIC16C8X PINOUT DESCRIPTION
DIP No. 16 15 SOIC No. 16 15 I/O/P Type I O Buffer Type Description
ST/CMOS (3) Oscillator crystal input/external clock source input. -- Oscillator crystal output. Connects to crystal or resonator in crystal oscillator mode. In RC mode, OSC2 pin outputs CLKOUT which has 1/4 the frequency of OSC1, and denotes the instruction cycle rate. Master clear (reset) input/programming voltage input. This pin is an active low reset to the device. PORTA is a bi-directional I/O port.
MCLR
4
4
I/P
ST
RA0 RA1 RA2 RA3 RA4/T0CKI
17 18 1 2 3
17 18 1 2 3
I/O I/O I/O I/O I/O
TTL TTL TTL TTL ST Can also be selected to be the clock input to the TMR0 timer/counter. Output is open drain type. PORTB is a bi-directional I/O port. PORTB can be software programmed for internal weak pull-up on all inputs.
RB0/INT RB1 RB2 RB3 RB4 RB5 RB6 RB7 VSS VDD Legend: I= input
6 7 8 9 10 11 12 13 5 14
6 7 8 9 10 11 12 13 5 14
I/O I/O I/O I/O I/O I/O I/O I/O P P
TTL/ST (1) TTL TTL TTL TTL TTL TTL/ST (2) TTL/ST (2) -- --
RB0/INT can also be selected as an external interrupt pin.
Interrupt on change pin. Interrupt on change pin. Interrupt on change pin. Serial programming clock. Interrupt on change pin. Serial programming data. Ground reference for logic and I/O pins. Positive supply for logic and I/O pins.
O = output I/O = Input/Output P = power -- = Not used TTL = TTL input ST = Schmitt Trigger input Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt (except PIC16C84, which remains TTL). 2: This buffer is a Schmitt Trigger input when used in serial programming mode. 3: This buffer is a Schmitt Trigger input when configured in RC oscillator mode and a CMOS input otherwise.
(c) 1995 Microchip Technology Inc.
DS30081F-page 9
PIC16C8X
3.1 Clocking Scheme/Instruction Cycle 3.2 Instruction Flow/Pipelining
The clock input (from OSC1) is internally divided by four to generate four non-overlapping quadrature clocks namely Q1, Q2, Q3 and Q4. Internally, the program counter (PC) is incremented every Q1, the instruction is fetched from the program memory and latched into the instruction register in Q4. The instruction is decoded and executed during the following Q1 through Q4. The clocks and instruction execution flow is shown in Figure 3-2. An "Instruction Cycle" consists of four Q cycles (Q1, Q2, Q3 and Q4). The instruction fetch and execute are pipelined such that fetch takes one instruction cycle while decode and execute takes another instruction cycle. However, due to the pipelining, each instruction effectively executes in one cycle. If an instruction causes the program counter to change (e.g., GOTO) then two cycles are required to complete the instruction (Example 3-1). A fetch cycle begins with the Program Counter (PC) incrementing in Q1. In the execution cycle, the fetched instruction is latched into the "Instruction Register" in cycle Q1. This instruction is then decoded and executed during the Q2, Q3, and Q4 cycles. Data memory is read during Q2 (operand read) and written during Q4 (destination write).
FIGURE 3-2:
CLOCK/INSTRUCTION CYCLE
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1 Q1 Q2 Q3 Q4 PC OSC2/CLKOUT (RC mode)
PC PC+1 PC+2
Internal phase clock
Fetch INST (PC) Execute INST (PC-1)
Fetch INST (PC+1) Execute INST (PC)
Fetch INST (PC+2) Execute INST (PC+1)
EXAMPLE 3-1:
1. MOVLW 55h 2. MOVWF PORTB 3. CALL 4. BSF SUB_1
INSTRUCTION PIPELINE FLOW
Fetch 1 Execute 1 Fetch 2 Execute 2 Fetch 3 Execute 3 Fetch 4 Flush Fetch SUB_1 Execute SUB_1
PORTA, BIT3
All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction is "flushed" from the pipeline while the new instruction is being fetched and then executed.
DS30081F-page 10
(c) 1995 Microchip Technology Inc.
PIC16C8X
4.0 MEMORY ORGANIZATION
There are two memory blocks in the PIC16C8X. These are the program memory and the data memory. Each block has its own bus, so that access to each block can occur during the same oscillator cycle. The data memory can further be broken down into the general purpose RAM and the Special Function Registers (SFRs). The operation of the SFRs that control the "core" are described here. The SFRs used to control the peripheral modules are described in the section discussing each individual peripheral module. The data memory area also contains the data EEPROM memory. This memory is not directly mapped into the data memory, but is indirectly mapped. That is an indirect address pointer specifies the address of the data EEPROM memory to read/write. The 64 bytes of data EEPROM memory have the address range 0h-3Fh. More details on the EEPROM memory can be found in Section 7.0.
FIGURE 4-1: PROGRAM MEMORY MAP AND STACK
PC<12:0> 13 CALL, RETURN RETFIE, RETLW Stack Level 1
* * *
Stack Level 8 Reset Vector Peripheral Interrupt Vector
0000h 0004h
User Memory Space
1FFh (PIC16C83, PIC16CR83)
4.1
Program Memory Organization
3FFh (PIC16C84, PIC16C84A, PIC16CR84)
The PIC16CXX has a 13-bit program counter capable of addressing an 8K x 14 program memory space. For the PIC16C83 and PIC16CR83 only the first 512 x 14 (0000h-01FFh) are physically implemented, and for the PIC16C84, PIC16C84A, and PIC16CR84 only the first 1K x 14 (0000h-03FFh) are physically implemented. Accessing a location above the physically implemented address will cause a wraparound. For example, for the PIC16C84 locations 20h, 420h, 820h, C20h, 1020h, 1420h, 1820h, and 1C20h will be the same instruction. The reset vector is at 0000h and the interrupt vector is at 0004h (Figure 4-1).
1FFFh
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4.2 Data Memory Organization
4.2.2 SPECIAL FUNCTION REGISTERS The data memory is partitioned into two areas. The first is the Special Function Registers (SFR) area, while the second is the General Purpose Registers (GPR) area. The SFRs control the operation of the device. Portions of data memory are banked. This is for both the SFR area and the GPR area. The GPR area is banked to allow greater than 116 bytes of general purpose RAM. The banked areas of the SFR are for the registers that control the peripheral functions. Banking requires the use of control bits for bank selection. These control bits are located in the STATUS Register. Figure 4-2 shows the data memory map organization. Instructions MOVWF and MOVF can move values from the W register to any location in the register file ("F"), and vice-versa. The entire data memory can be accessed either directly using the absolute address of each register file or indirectly through the File Select Register (FSR) (Section 4.4). Indirect addressing uses the present value of the RP1:RP0 bits for access into the banked areas of data memory. Data memory is partitioned into two banks which contain the general purpose registers and the special function registers. Bank 0 is selected by clearing the RP0 bit (STATUS<5>). Setting the RP0 bit selects Bank 1. Each Bank extends up to 7Fh (128 bytes). The lower locations of each Bank are reserved for the Special Function Registers. Above the Special Function Registers are General Purpose Registers implemented as static RAM. (Figure 4-2) 4.2.1 GENERAL PURPOSE REGISTER FILE The Special Function Registers (Figure 4-2 and Table 4-1) are used by the CPU and Peripheral functions to control the device operation. These registers are static RAM. The special function registers can be classified into two sets, core and peripheral. Those associated with the "core" functions are described in this section. Those related to the operation of the peripheral features are described in the section for that specific feature.
FIGURE 4-2:
File Address 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch
REGISTER FILE MAP
File Address Indirect addr.(1) OPTION PCL STATUS FSR TRISA TRISB EECON1 EECON2(1) PCLATH INTCON 80h 81h 82h 83h 84h 85h 86h 87h EEDATA EEADR PCLATH INTCON 88h 89h 8Ah 8Bh 8Ch
Indirect addr.(1) TMR0 PCL STATUS FSR PORTA PORTB
All devices have some amount of General Purpose Register (GPR) area. Each GPR is 8-bits wide and is accessed either directly, or indirectly through the FSR (Section 4.4). Architecturally, the GPR area starts at address 0Ch for bank 0 and 8Ch for bank 1. When more than 116 bytes of GPR are present on the device, banking must be performed to access the additional memory space. PIC16C8X devices have up to 68 bytes of GPR memory, and therefore do not require banking of the GPR memory. Any access to Bank 1 will cause the access to occur in Bank 0. That is, the MSb of the 8-bit direct address will be ignored.
2Fh (2) 30h (2)
36 / 68 General Purpose registers (SRAM)
Mapped (accesses) in Bank 0
AFh (2) B0h(2)
4Fh (2) 50h (2)
CFh (2) D0h (2)
7Fh Bank 0 Bank 1
FFh
Unimplemented data memory location; read as '0'. Note 1: Not a physical register. 2: The address depends on the device used. Devices with 36 bytes end at 2Fh, devices with 68 bytes end at 4Fh.
DS30081F-page 12
(c) 1995 Microchip Technology Inc.
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PIC16C8X
TABLE 4-1: REGISTER FILE SUMMARY
Value on Power-on Reset Value on all other resets (Note3)
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bank 0 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh Bank 1 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 0Ah 0Bh EECON1 EECON2 PCLATH INTCON INDF OPTION PCL STATUS (2) FSR TRISA TRISB Uses contents of FSR to address data memory (not a physical register) RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 ---- ---1111 1111 0000 0000 PD Z DC C 0001 1xxx xxxx xxxx ---1 1111 1111 1111 ---- ---EEIF WRERR WREN WR RD ---0 x000 ---- ------0 0000 INTF RBIF ---- ---1111 1111 0000 0000 000q quuu uuuu uuuu ---1 1111 1111 1111 ---- ------0 q000 ---- ------0 0000 EEDATA EEADR PCLATH INTCON INDF TMR0 PCL STATUS FSR PORTA PORTB
(2)
Uses contents of FSR to address data memory (not a physical register) 8-bit real-time clock/counter Low order 8 bits of the Program Counter (PC) IRP RP1 RP0 TO PD Z DC C
---- ---xxxx xxxx 0000 0000 0001 1xxx xxxx xxxx
---- ---uuuu uuuu 0000 0000 000q quuu uuuu uuuu ---u uuuu uuuu uuuu ---- ---uuuu uuuu uuuu uuuu ---0 0000 0000 000u
Indirect data memory address pointer 0 -- RB7 -- RB6 -- RB5 RA4/T0CKI RB4 RA3 RB3 RA2 RB2 RA1 RB1 RA0 RB0/INT
---x xxxx xxxx xxxx ---- ---xxxx xxxx xxxx xxxx
Unimplemented location, read as '0' EEPROM data register EEPROM address register -- GIE -- EEIE -- T0IE Write buffer for upper 5 bits of the PC (1) INTE RBIE T0IF INTF RBIF
---0 0000 0000 000x
Low order 8 bits of Program Counter (PC) IRP RP1 RP0 TO
Indirect data memory address pointer 0 -- -- -- PORTA data direction register
PORTB data direction register Unimplemented location, read as '0' -- -- --
EEPROM control register 2 (not a physical register) -- GIE -- EEIE -- T0IE Write buffer for upper 5 bits of the PC (1) INTE RBIE T0IF
(c) 1995 Microchip Technology Inc.
DS30081F-page 13
PIC16C8X
4.2.2.1 STATUS REGISTER The STATUS register contains the arithmetic status of the ALU, the RESET status and the bank select bit for data memory. As with any register, the STATUS register can be the destination for any instruction. If the STATUS register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bits are set or cleared according to device logic. Furthermore, the TO and PD bits are not writable. Therefore, the result of an instruction with the STATUS register as destination may be different than intended. For example, CLRF STATUS will clear the upper-three bits and set the Z bit. This leaves the STATUS register as 000u u1uu (where u = unchanged). Only the BCF, BSF, SWAPF and MOVWF instructions should be used to alter the STATUS register (Table 9-2) because these instructions do not affect any status bit. Note 1: The IRP and RP1 bits (STATUS<7:6>) are not used by the PIC16C8X and should be programmed as cleared. Use of these bits as general purpose R/W bits is NOT recommended, since this may affect upward compatibility with future products. Note 2: The C and DC bits operate as a borrow and digit borrow out bit, respectively, in subtraction. See the SUBLW and SUBWF instructions for examples. Note 3: When the STATUS register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. The specified bit(s) will be updated according to device logic.
DS30081F-page 14
(c) 1995 Microchip Technology Inc.
PIC16C8X
FIGURE 4-3:
R/W-0 IRP bit7
STATUS REGISTER (ADDRESS 03h, 83h)
R/W-0 RP0 R-1 R-1 R/W-x Z R/W-x DC R/W-x C bit0
R/W-0 RP1
TO
PD
R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' - n = Value at POR reset
bit 7:
IRP: Register Bank Select bit (used for indirect addressing) 0 = Bank 0, 1 (00h - FFh) 1 = Bank 2, 3 (100h - 1FFh) The IRP bit is not used by the PIC16C8X. IRP should be maintained clear.
bit 6-5: RP1:RP0: Register Bank Select bits (used for direct addressing) 00 = Bank 0 (00h - 7Fh) 01 = Bank 1 (80h - FFh) 10 = Bank 2 (100h - 17Fh) 11 = Bank 3 (180h - 1FFh) Each bank is 128 bytes. Only bit RP0 is used by the PIC16C8X. RP1 should be maintained clear. bit 4: TO: Time-out bit 1 = After power-up, CLRWDT instruction, or SLEEP instruction 0 = A WDT time-out occurred PD: Power-down bit 1 = After power-up or by the CLRWDT instruction 0 = By execution of the SLEEP instruction Z: Zero bit 1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero DC: Digit carry/borrow bit (for ADDWF and ADDLW instructions) (For borrow the polarity is reversed) 1 = A carry-out from the 4th low order bit of the result occurred 0 = No carry-out from the 4th low order bit of the result C: Carry/borrow bit (for ADDWF and ADDLW instructions) 1 = A carry-out from the most significant bit of the result occurred 0 = No carry-out from the most significant bit of the result occurred Note: For borrow the polarity is reversed. A subtraction is executed by adding the two's complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low order bit of the source register.
bit 3:
bit 2:
bit 1:
bit 0:
(c) 1995 Microchip Technology Inc.
DS30081F-page 15
PIC16C8X
4.2.2.2 OPTION REGISTER Note: The OPTION register is a readable and writable register which contains various control bits to configure the TMR0/WDT prescaler, the external INT interrupt, TMR0, and the weak pull-ups on PORTB. When the prescaler is assigned to the WDT (PSA = '1'), TMR0 has a 1:1 prescaler assignment.
FIGURE 4-4:
R/W-1 RBPU bit7
OPTION REGISTER (ADDRESS 81h)
R/W-1 T0CS R/W-1 T0SE R/W-1 PSA R/W-1 PS2 R/W-1 PS1 R/W-1 PS0 bit0
R/W-1 INTEDG
R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' - n = Value at POR reset
bit 7:
RBPU: PORTB Pull-up Enable bit 1 = PORTB pull-ups are disabled 0 = PORTB pull-ups are enabled (by individual port latch values) INTEDG: Interrupt Edge Select bit 1 = Interrupt on rising edge of RB0/INT pin 0 = Interrupt on falling edge of RB0/INT pin T0CS: TMR0 Clock Source Select bit 1 = Transition on RA4/T0CKI pin 0 = Internal instruction cycle clock (CLKOUT) T0SE: TMR0 Source Edge Select bit 1 = Increment on high-to-low transition on RA4/T0CKI pin 0 = Increment on low-to-high transition on RA4/T0CKI pin PSA: Prescaler Assignment bit 1 = Prescaler assigned to the WDT 0 = Prescaler assigned to TMR0
bit 6:
bit 5:
bit 4:
bit 3:
bit 2-0: PS2:PS0: Prescaler Rate Select bits
Bit Value 000 001 010 011 100 101 110 111 TMR0 Rate 1:2 1:4 1:8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256 WDT Rate 1:1 1:2 1:4 1:8 1 : 16 1 : 32 1 : 64 1 : 128
DS30081F-page 16
(c) 1995 Microchip Technology Inc.
PIC16C8X
4.2.2.3 INTCON REGISTER Note: The INTCON register is a readable and writable register which contains the various enable bits for all interrupt sources. Interrupt flag bits get set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>).
FIGURE 4-5:
R/W-0 GIE bit7
INTCON REGISTER (ADDRESS 0Bh, 8Bh)
R/W-0 T0IE R/W-0 INTE R/W-0 RBIE R/W-0 T0IF R/W-0 INTF R/W-x RBIF bit0
R/W-0 EEIE
R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' - n = Value at POR reset
bit 7:
GIE: Global Interrupt Enable bit 1 = Enables all un-masked interrupts 0 = Disables all interrupts Note: For the operation of the interrupt structure, please refer to Section 8.5. EEIE: EE Write Complete Interrupt Enable bit 1 = Enables the EE write complete interrupt 0 = Disables the EE write complete interrupt T0IE: TMR0 Overflow Interrupt Enable bit 1 = Enables the TMR0 interrupt 0 = Disables the TMR0 interrupt INTE: RB0/INT Interrupt Enable bit 1 = Enables the RB0/INT interrupt 0 = Disables the RB0/INT interrupt RBIE: RB Port Change Interrupt Enable bit 1 = Enables the RB port change interrupt 0 = Disables the RB port change interrupt T0IF: TMR0 overflow interrupt flag bit 1 = TMR0 has overflowed (must be cleared in software) 0 = TMR0 did not overflow INTF: RB0/INT Interrupt Flag bit 1 = The RB0/INT interrupt occurred 0 = The RB0/INT interrupt did not occur RBIF: RB Port Change Interrupt Flag bit 1 = When at least one of the RB7:RB4 pins changed state (must be cleared in software) 0 = None of the RB7:RB4 pins have changed state
bit 6:
bit 5:
bit 4:
bit 3:
bit 2:
bit 1:
bit 0:
(c) 1995 Microchip Technology Inc.
DS30081F-page 17
PIC16C8X
4.3 PCL and PCLATH
4.3.2 STACK The Program Counter (PC) is 13-bits wide. The low byte is the PCL register, which is a readable and writable register. The high byte of the PC (PC<12:8>) is not directly readable nor writable and comes from the PCLATH register. The PCLATH (PC latch high) register is a holding register for PC<12:8>. The contents of PCLATH are transferred to the upper byte of the program counter when the PC is loaded with a new value. This occurs during a CALL, GOTO or a write to PCL. The high bits of PC are loaded from PCLATH as shown in Figure 4-6. The PIC16CXX has an 8 deep x 13-bit wide hardware stack (Figure 4-1). The stack space is not part of either program or data space and the stack pointer is not readable or writable. The entire 13-bit PC is PUSH'ed onto the stack when a CALL instruction is executed or an interrupt is acknowledged. The stack is POP'ed in the event of a RETURN, RETLW or a RETFIE instruction execution. PCLATH is not affected by a PUSH or a POP operation. The stack operates as a circular buffer. That is, after the stack has been PUSH'ed eight times, the ninth push overwrites the value that was stored from the first push. The tenth push overwrites the second push (and so on). If the stack is effectively POP'ed nine times, the PC value is the same as the value from the first POP.
INST with PCL as dest 5 PCLATH<4:0> 8 ALU result
FIGURE 4-6:
PCH 12 PC
LOADING OF PC IN DIFFERENT SITUATIONS
PCL 87 0
Note 1: There are no status bits to indicate stack overflow or stack underflow conditions. Note 2: There are no instructions mnemonics called PUSH or POP. These are actions that occur from the execution of the CALL, RETURN, RETLW, and RETFIE instructions, or the vectoring to an interrupt address 4.3.3 PROGRAM MEMORY PAGING
PCLATH PCH 12 11 10 PC 2 PCLATH<4:3> 11 Opcode <10:0> PCL 87 0 GOTO, CALL
PCLATH
4.3.1
COMPUTED GOTO
A computed GOTO is accomplished by adding an offset to the program counter (ADDWF PCL). When doing a table read using a computed GOTO method, care should be exercised if the table location crosses a PCL memory boundary (each 256 byte block). Refer to the application note "Implementing a Table Read" (AN556).
The PIC16C83 and PIC16CR83 have 512 words of program memory. The PIC16C84, PIC16C84A, and PIC16CR84 have 1K of program memory. The CALL and GOTO instructions have an 11-bit address range. This 11-bit address range allows a branch within a 2K program memory page size. For future PIC16C8X program memory expansion, there must be another two bits to specify the program memory page. These paging bits come from the PCLATH<4:3> bits (Figure 4-6). When doing a CALL or a GOTO instruction, the user must ensure that these page bits (PCLATH<4:3>) are programmed to the desired program memory page. If a CALL instruction (or interrupt) is executed, the entire 13-bit PC is pushed onto the stack. Therefore, manipulation of the PCLATH<4:3> is not required for the return instructions (which POPs the PC from the stack). Note: The PIC16C8X ignores the PCLATH<4:3> bits, which are used for program memory pages 1, 2 and 3 (0800h - 1FFFh). The use of PCLATH<4:3> as general purpose R/W bits is not recommended since this may affect upward compatibility with future products.
DS30081F-page 18
(c) 1995 Microchip Technology Inc.
PIC16C8X
4.4 Indirect Addressing, INDF and FSR Registers EXAMPLE 4-1:
movlw movwf clrf incf btfss goto :
INDIRECT ADDRESSING
0x20 FSR INDF FSR FSR,4 NEXT ;initialize pointer ; to RAM ;clear INDF register ;inc pointer ;all done? ;NO, clear next ;YES, continue
The INDF register is not a physical register and is used in conjunction with the FSR register to perform indirect addressing. Indirect addressing is possible by using the INDF register. Any instruction using the INDF register actually accesses data pointed to by the file select register (FSR). Reading INDF itself indirectly (FSR = 0) will produce 00h. Writing to the INDF register indirectly results in a no-operation (although status bits may be affected). An effective 9-bit address is obtained by concatenating the 8-bit FSR register and the IRP bit (STATUS<7>), as shown in Figure 4-7. However, IRP is not used in the PIC16C8X. A simple program to clear RAM locations 20h-2Fh using indirect addressing is shown in Example 4-1.
NEXT
CONTINUE
FIGURE 4-7:
DIRECT/INDIRECT ADDRESSING
Direct Addressing Indirect Addressing 0 IRP 7 (FSR) 0
RP1 RP0
6
from opcode
bank select
location select
bank select
location select
00 00h 0Bh 0Ch 2Fh (1) 30h (1) 4Fh (2) 50h (2) 7Fh Bank 0
01
10
11 00h
not used
mapped in bank 0
7Fh Bank 1 Bank 2 Bank 3
Note 1: PIC16C83, PIC16CR83, and PIC16C84 devices. 2: PIC16C84A and PIC16CR84 devices 3: For memory map detail see Figure 4-1.
(c) 1995 Microchip Technology Inc.
DS30081F-page 19
PIC16C8X
NOTES:
DS30081F-page 20
(c) 1995 Microchip Technology Inc.
PIC16C8X
5.0 I/O PORTS
EXAMPLE 5-1:
CLRF PORTA
INITIALIZING PORTA
; ; ; ; ; ; ; ; ; ; ; Initialize PORTA by setting output data latches Select Bank 1 Value used to initialize data direction Set RA<3:0> as inputs RA4 as outputs TRISA<7:5> are always read as '0'.
The PIC16C8X family has two ports, PORTA and PORTB. Some port pins are multiplexed with an alternate function for other features on the device.
5.1
PORTA and TRISA Registers
BSF MOVLW
STATUS, RP0 0x0F
PORTA is a 5-bit wide latch. RA4 is a Schmitt Trigger input and an open drain output. All other RA port pins have TTL input levels and full CMOS output drivers. All pins have data direction bits (TRIS registers) which can configure these pins as output or input. A '1' on any bit in the TRISA register puts the corresponding output driver in a hi-impedance mode. A '0' on any bit in the TRISA register puts the contents of the output latch on the selected pin(s). Reading the PORTA register reads the status of the pins whereas writing to it will write to the port latch. All write operations are read-modify-write operations. So a write to a port implies that the port pins are first read, then this value is modified and written to the port data latch. The RA4 pin is multiplexed with the TMR0 clock input.
MOVWF
TRISA
FIGURE 5-2:
Data bus WR PORT
BLOCK DIAGRAM OF PIN RA4
D
Q Q
CK
N Data Latch VSS
D Q Q
RA4 pin
FIGURE 5-1:
Data bus WR Port
BLOCK DIAGRAM OF PINS RA3:RA0
Q VDD
WR TRIS
CK
TRIS Latch
Schmitt Trigger input buffer
D
RD TRIS
Q D EN EN
CK
Q
P
Data Latch N D WR TRIS Q VSS CK Q Note: I/O pin has protection diodes to VSS only. TRIS Latch TTL input buffer I/O pin RD PORT TMR0 clock input
Note:
RD TRIS Q D
EN RD PORT
For the PIC16C84 Only: For crystal oscillator configurations operating below 500 kHz, the device may generate a spurious internal Q-clock when PORTA<0> switches state. This does not occur with an external clock in RC mode. To avoid this, the RA0 pin should be kept static, i.e. in input/output mode, pin RA0 should not be toggled.
Note: I/O pins have protection diodes to VDD and VSS.
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DS30081F-page 21
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TABLE 5-1:
Name RA0 RA1 RA2 RA3 RA4/T0CKI
PORTA FUNCTIONS
Bit0 bit0 bit1 bit2 bit3 bit4 Buffer Type TTL TTL TTL TTL ST Function
Input/output Input/output Input/output Input/output Input/output or external clock input for TMR0. Output is open drain type. Legend: TTL = TTL input, ST = Schmitt Trigger input
TABLE 5-2:
Address 05h 85h Name PORTA TRISA
SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
Bit 7 -- -- Bit 6 -- -- Bit 5 -- -- Bit 4 RA4/T0CKI TRISA4 Bit 3 RA3 TRISA3 Bit 2 RA2 TRISA2 Bit 1 RA1 TRISA1 Bit 0 RA0 TRISA0 Value on Power-on Reset ---x xxxx ---1 1111 Value on all other resets ---u uuuu ---1 1111
Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are unimplemented, read as '0'
DS30081F-page 22
(c) 1995 Microchip Technology Inc.
PIC16C8X
5.2 PORTB and TRISB Registers
PORTB is an 8-bit wide bi-directional port. The corresponding data direction register is TRISB. A '1' on any bit in the TRISB register puts the corresponding output driver in a hi-impedance mode. A '0' on any bit in the TRISB register puts the contents of the output latch on the selected pin(s). Each of the PORTB pins have a weak internal pull-up. A single control bit can turn on all the pull-ups. This is done by clearing the RBPU (OPTION<7>) bit. The weak pull-up is automatically turned off when the port pin is configured as an output. The pull-ups are disabled on a Power-on Reset. Four of PORTB's pins, RB7:RB4, have an interrupt on change feature. Only pins configured as inputs can cause this interrupt to occur (i.e., any RB7:RB4 pin configured as an output is excluded from the interrupt on change comparison). The pins value in input mode are compared with the old value latched on the last read of PORTB. The "mismatch" outputs of the pins are OR'ed together to generate the RB port change interrupt. This interrupt can wake the device from SLEEP. The user, in the interrupt service routine, can clear the interrupt in the following manner: a) b) Read (or write) PORTB. This will end the mismatch condition. Clear flag bit RBIF.
A mismatch condition will continue to set the RBIF bit. Reading PORTB will end the mismatch condition, and allow the RBIF bit to be cleared. This interrupt on mismatch feature, together with software configurable pull-ups on these four pins allow easy interface to a key pad and make it possible for wake-up on key-depression (see AN552 in the Embedded Control Handbook). Note 1: For the PIC16C84 Only; If a change on the I/O pin should occur when a read operation of PORTB is being executed (start of the Q2 cycle), the RBIF interrupt flag bit may not be set. Note 2: For all other PIC16C8X devices; For a change on the I/O pin to be recognized, the pulse width must be at least TCY wide. The interrupt on change feature is recommended for wake-up on key depression operation and operations where PORTB is only used for the interrupt on change feature. Polling of PORTB is not recommended while using the interrupt on change feature.
FIGURE 5-3:
BLOCK DIAGRAM OF PINS RB7:RB4
VDD
RBPU Data Latch D CK TRIS Latch D WR TRIS CK Q Q
weak P pull-up
Data bus WR Port
FIGURE 5-4:
I/O pin RBPU
BLOCK DIAGRAM OF PINS RB3:RB0 (PIC16C84 ONLY)
VDD weak P pull-up Data Latch D CK TRIS Latch D Q Q I/O pin
Data bus TTL Input Buffer WR Port
RD TRIS
Latch Q D EN WR TRIS
CK
Input Buffer
RD Port Set RBIF From other RB7:RB4 pins
RD TRIS Q D EN RD Port RB0/INT(3) RD Port Note 1: TRISB = '1' enables weak pull-up (if RBPU = '0' in the OPTION register). 2: I/O pins have diode protection to VDD and VSS. Q D EN
RD Port Note 1: TRISB = '1' enables weak pull-up (if RBPU = '0' in the OPTION register). 2: I/O pins have diode protection to VDD and VSS.
(c) 1995 Microchip Technology Inc.
DS30081F-page 23
PIC16C8X
FIGURE 5-5: BLOCK DIAGRAM OF PINS RB3:RB0 (ALL OTHER PIC16C8X DEVICES)
VDD RBPU(2) Data Latch D Q CK TRIS Latch D Q WR TRIS CK I/O pin(1) weak P pull-up
EXAMPLE 5-2:
CLRF PORTB
INITIALIZING PORTB
; ; ; ; ; ; ; ; ; ; Initialize PORTB by setting output data latches Select Bank 1 Value used to initialize data direction Set RB<3:0> as inputs RB<5:4> as outputs RB<7:6> as inputs
BSF MOVLW
STATUS, RP0 0xCF
Data bus WR Port
MOVWF
TRISB
TTL Input Buffer
RD TRIS Q RD Port D EN
RB0/INT Schmitt Trigger Buffer Note 1: I/O pins have diode protection to VDD and VSS. 2: TRISB = '1' enables weak pull-up if RBPU = '0' (OPTION<7>). RD Port
TABLE 5-3:
Name RB0/INT
PORTB FUNCTIONS
Bit bit0 Buffer Type TTL/ST(1) I/O Consistency Function
Input/output pin or external interrupt input. Internal software programmable weak pull-up. RB1 bit1 TTL Input/output pin. Internal software programmable weak pull-up. RB2 bit2 TTL Input/output pin. Internal software programmable weak pull-up. RB3 bit3 TTL Input/output pin. Internal software programmable weak pull-up. RB4 bit4 TTL Input/output pin (with interrupt on change). Internal software programmable weak pull-up. RB5 bit5 TTL Input/output pin (with interrupt on change). Internal software programmable weak pull-up. RB6 bit6 TTL/ST(2) Input/output pin (with interrupt on change). Internal software programmable weak pull-up. Serial programming clock. RB7 bit7 TTL/ST(2) Input/output pin (with interrupt on change). Internal software programmable weak pull-up. Serial programming data. Legend: TTL = TTL input, ST = Schmitt Trigger. Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt, except for the PIC16C84, which remains TTL. 2: This buffer is a Schmitt Trigger input when used in serial programming mode.
TABLE 5-4:
Address 06h 86h 81h Name PORTB TRISB OPTION
SUMMARY OF REGISTERS ASSOCIATED WITH PORTB
Bit 7 RB7 TRISB7 RBPU Bit 6 RB6 TRISB6 INTEDG Bit 5 RB5 TRISB5 T0CS Bit 4 RB4 TRISB4 T0SE Bit 3 RB3 TRISB3 PSA Bit 2 RB2 TRISB2 PS2 Bit 1 RB1 TRISB1 PS1 Bit 0 RB0/INT TRISB0 PS0 Value on Power-on Reset xxxx xxxx 1111 1111 1111 1111 Value on all other resets uuuu uuuu 1111 1111 1111 1111
Legend: x = unknown, u = unchanged. Shaded cells are not used by PORTB.
DS30081F-page 24
(c) 1995 Microchip Technology Inc.
PIC16C8X
5.3
5.3.1
I/O Programming Considerations
BI-DIRECTIONAL I/O PORTS
5.3.2
SUCCESSIVE OPERATIONS ON I/O PORTS
Any instruction which writes, operates internally as a read followed by a write operation. The BCF and BSF instructions, for example, read the register into the CPU, execute the bit operation and write the result back to the register. Caution must be used when these instructions are applied to a port with both inputs and outputs defined. For example, a BSF operation on bit5 of PORTB will cause all eight bits of PORTB to be read into the CPU. Then the BSF operation takes place on bit5 and PORTB is written to the output latches. If another bit of PORTB is used as a bi-directional I/O pin (i.e., bit0) and it is defined as an input at this time, the input signal present on the pin itself would be read into the CPU and rewritten to the data latch of this particular pin, overwriting the previous content. As long as the pin stays in the input mode, no problem occurs. However, if bit0 is switched into output mode later on, the content of the data latch is unknown. Reading the port register, reads the values of the port pins. Writing to the port register writes the value to the port latch. When using read-modify-write instructions (i.e., BCF, BSF, etc.) on a port, the value of the port pins is read, the desired operation is done to this value, and this value is then written to the port latch. A pin actively outputting a Low or High should not be driven from external devices at the same time in order to change the level on this pin ("wired-or", "wired-and"). The resulting high output current may damage the chip.
The actual write to an I/O port happens at the end of an instruction cycle, whereas for reading, the data must be valid at the beginning of the instruction cycle (Figure 5-6). Therefore, care must be exercised if a write followed by a read operation is carried out on the same I/O port. The sequence of instructions should be such that the pin voltage stabilizes (load dependent) before the next instruction which causes that file to be read into the CPU is executed. Otherwise, the previous state of that pin may be read into the CPU rather than the new state. When in doubt, it is better to separate these instructions with a NOP or another instruction not accessing this I/O port. Example 5-3 shows the effect of two sequential readmodify-write instructions (e.g., BCF, BSF, etc.) on an I/O port.
EXAMPLE 5-3:
READ-MODIFY-WRITE INSTRUCTIONS ON AN I/O PORT
;Initial PORT settings: PORTB<7:4> Inputs ; PORTB<3:0> Outputs ;PORTB<7:6> have external pull-ups and are ;not connected to other circuitry ; ; PORT latch PORT pins ; ---------- --------BCF PORTB, 7 ; 01pp ppp 11pp ppp BCF PORTB, 6 ; 10pp ppp 11pp ppp BSF STATUS, RP0 ; BCF TRISB, 7 ; 10pp ppp 11pp ppp BCF TRISB, 6 ; 10pp ppp 10pp ppp ; ;Note that the user may have expected the ;pin values to be 00pp ppp. The 2nd BCF ;caused RB7 to be latched as the pin value ;(high).
FIGURE 5-6:
SUCCESSIVE I/O OPERATION
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 PC PC + 1 MOVF PORTB,W NOP NOP PC + 2 PC + 3
Note: This example shows as write to PORTB followed by a read from PORTB. Note that: data setup time = (0.25 TCY - TPD) where:TCY = instruction cycle TPD = propagation delay Therefore, at higher clock frequencies, a write followed by a read may be problematic.
Instruction fetched RB7:RB0
MOVWF PORTB write to PORTB
Port pin sampled here Instruction executed MOVWF PORTB write to PORTB MOVF PORTB,W NOP NOP
(c) 1995 Microchip Technology Inc.
DS30081F-page 25
PIC16C8X
NOTES:
DS30081F-page 26
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PIC16C8X
6.0 TIMER0 MODULE AND TMR0 REGISTER
edge select bit, T0SE (OPTION<4>). Clearing bit T0SE selects the rising edge. Restrictions on the external clock input are discussed in detail in Section 6.2. The prescaler is shared between the Timer0 Module and the Watchdog Timer. The prescaler assignment is controlled, in software, by control bit PSA (OPTION<3>). Clearing bit PSA will assign the prescaler to the Timer0 Module. The prescaler is not readable or writable. When the prescaler (Section 6.3) is assigned to the Timer0 Module, the prescale value (1:2, 1:4, ..., 1:256) is software selectable.
The Timer0 module timer/counter has the following features: * * * * * * 8-bit timer/counter Readable and writable 8-bit software programmable prescaler Internal or external clock select Interrupt on overflow from FFh to 00h Edge select for external clock
Timer mode is selected by clearing the T0CS bit (OPTION<5>). In timer mode, the Timer0 module (Figure 6-1) will increment every instruction cycle (without prescaler). If the TMR0 register is written, the increment is inhibited for the following two cycles (Figure 6-2 and Figure 6-3). The user can work around this by writing an adjusted value to the TMR0 register. Counter mode is selected by setting the T0CS bit (OPTION<5>). In this mode TMR0 will increment either on every rising or falling edge of pin RA4/T0CKI. The incrementing edge is determined by the T0 source
6.1
TMR0 Interrupt
The TMR0 interrupt is generated when the TMR0 register overflows from FFh to 00h. This overflow sets the T0IF bit (INTCON<2>). The interrupt can be masked by clearing enable bit T0IE (INTCON<5>). The T0IF bit must be cleared in software by the Timer0 Module interrupt service routine before re-enabling this interrupt. The TMR0 interrupt (Figure 6-4) cannot wake the processor from SLEEP since the timer is shut off during SLEEP.
FIGURE 6-1:
TMR0 BLOCK DIAGRAM
Data bus FOSC/4 0 1 1 PSout Sync with Internal clocks (2 cycle delay) Set bit T0IF on Overflow 8 TMR0 register PSout
RA4/T0CKI pin T0SE
Programmable Prescaler 3 PS2, PS1, PS0 T0CS
0
PSA
Note 1: Bits T0CS, T0SE, PS2, PS1, PS0 and PSA are located in the OPTION register. 2: The prescaler is shared with the Watchdog Timer (Figure 6-6)
FIGURE 6-2:
TMR0 TIMING: INTERNAL CLOCK/NO PRESCALER
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
PC Instruction Fetch T0
PC-1
PC MOVWF TMR0
PC+1 MOVF TMR0,W
PC+2 MOVF TMR0,W
PC+3 MOVF TMR0,W
PC+4 MOVF TMR0,W
PC+5 MOVF TMR0,W
PC+6
TMR0
T0+1
T0+2
NT0
NT0
NT0
NT0+1
NT0+2
T0
Instruction Executed
Write TMR0 executed
Read TMR0 reads NT0
Read TMR0 reads NT0
Read TMR0 reads NT0
Read TMR0 reads NT0 + 1
Read TMR0 reads NT0 + 2
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DS30081F-page 27
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PIC16C8X
FIGURE 6-3: TMR0 TIMING: INTERNAL CLOCK/PRESCALE 1:2
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 PC Instruction Fetch TMR0 T0 PC-1 PC MOVWF TMR0 PC+1 MOVF TMR0,W PC+2 MOVF TMR0,W PC+3 MOVF TMR0,W PC+4 MOVF TMR0,W PC+5 MOVF TMR0,W PC+6
T0+1
NT0
NT0+1
Instruction Execute
Write TMR0 executed
Read TMR0 reads NT0
Read TMR0 reads NT0
Read TMR0 reads NT0
Read TMR0 reads NT0
Read TMR0 reads NT0 + 1
FIGURE 6-4:
TMR0 INTERRUPT TIMING
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1 CLKOUT(3) TMR0 timer T0IF bit 4 (INTCON<2>) GIE bit (INTCON<7>) INSTRUCTION FLOW PC Instruction fetched Instruction executed PC Inst (PC) Inst (PC-1) PC +1 Inst (PC+1) Dummy cycle Interrupt Latency(2) PC +1 0004h Inst (0004h) Dummy cycle 0005h Inst (0005h) Inst (0004h) FEh 1 FFh 1 00h 01h 02h
Inst (PC)
Note 1: T0IF interrupt flag is sampled here (every Q1). 2: Interrupt latency = 3.25Tcy, where Tcy = instruction cycle time. 3: CLKOUT is available only in RC oscillator mode. 4: The timer clock (after the synchronizer circuit) which increments the timer from FFh to 00h immediately sets the T0IF bit. The TMR0 register will roll over 3 Tosc cycles later.
DS30081F-page 28
(c) 1995 Microchip Technology Inc.
PIC16C8X
6.2 Using TMR0 with External Clock 6.3 Prescaler
When an external clock input is used for TMR0, it must meet certain requirements. The external clock requirement is due to internal phase clock (TOSC) synchronization. Also, there is a delay in the actual incrementing of the TMR0 register after synchronization. 6.2.1 EXTERNAL CLOCK SYNCHRONIZATION An 8-bit counter is available as a prescaler for the Timer0 Module, or as a postscaler for the Watchdog Timer (Figure 6-6). For simplicity, this counter is being referred to as "prescaler" throughout this data sheet. Note that there is only one prescaler available which is mutually exclusive between the Timer0 Module and the Watchdog Timer. Thus, a prescaler assignment for the Timer0 Module means that there is no prescaler for the Watchdog Timer, and vice-versa. The PSA and PS2:PS0 bits (OPTION<3:0>) determine the prescaler assignment and prescale ratio. When assigned to the Timer0 Module, all instructions writing to the Timer0 Module (e.g., CLRF 1, MOVWF 1, BSF 1,x ....etc.) will clear the prescaler. When assigned to WDT, a CLRWDT instruction will clear the prescaler along with the Watchdog Timer. The prescaler is not readable or writable.
When no prescaler is used, the external clock input is the same as the prescaler output. The synchronization of pin RA4/T0CKI with the internal phase clocks is accomplished by sampling the prescaler output on the Q2 and Q4 cycles of the internal phase clocks (Figure 6-5). Therefore, it is necessary for T0CKI to be high for at least 2Tosc (plus a small RC delay) and low for at least 2Tosc (plus a small RC delay). Refer to the electrical specification of the desired device. When a prescaler is used, the external clock input is divided by an asynchronous ripple counter type prescaler so that the prescaler output is symmetrical. For the external clock to meet the sampling requirement, the ripple counter must be taken into account. Therefore, it is necessary for T0CKI to have a period of at least 4Tosc (plus a small RC delay) divided by the prescaler value. The only requirement on T0CKI high and low time is that they do not violate the minimum pulse width requirement of 10 ns. Refer to parameters 40, 41 and 42 in the AC Electrical Specifications of the desired device. 6.2.2 TMR0 INCREMENT DELAY
Since the prescaler output is synchronized with the internal clocks, there is a small delay from the time the external clock edge occurs to the time the Timer0 Module is actually incremented. Figure 6-5 shows the delay from the external clock edge to the timer incrementing.
FIGURE 6-5:
TIMER0 TIMING WITH EXTERNAL CLOCK
Q1 Q2 Q3 Q4 Ext. Clock Input or Prescaler Out (Note 2) Ext. Clock/Prescaler Output After Sampling Increment TMR0 (Q4) TMR0 T0 T0 + 1 T0 + 2 (Note 3) Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Note 1: Delay from clock input change to TMR0 increment is 3Tosc to 7Tosc. (Duration of Q = Tosc). Therefore, the error in measuring the interval between two edges on TMR0 input = 4Tosc max. 2: External clock if no prescaler selected, Prescaler output otherwise. 3: The arrows indicate where sampling occurs. A small clock pulse may be missed by sampling.
(c) 1995 Microchip Technology Inc.
DS30081F-page 29
PIC16C8X
FIGURE 6-6: BLOCK DIAGRAM OF THE TMR0/WDT PRESCALER
Data Bus CLKOUT (= Fosc/4)
0 RA4/T0CKI pin 1 T0SE
M U X
1 0 M U X SYNC 2 Cycles
8 TMR0 register
T0CS
PSA
Set bit T0IF on overflow
0 M U X
8-bit Prescaler 8 8 - to - 1MUX PS2:PS0
Watchdog Timer
1
PSA 0 MUX 1 PSA
WDT Enable bit
WDT time-out Note: T0CS, T0SE, PSA, PS2:PS0 are bits in the OPTION register.
DS30081F-page 30
(c) 1995 Microchip Technology Inc.
PIC16C8X
6.3.1 SWITCHING PRESCALER ASSIGNMENT
EXAMPLE 6-2:
CLRWDT BSF MOVLW
The prescaler assignment is fully under software control (i.e., it can be changed "on the fly" during program execution). Note: To avoid an unintended device RESET, the following instruction sequence (Example 6-1) must be executed when changing the prescaler assignment from Timer0 to the WDT. This sequence must be taken even if the WDT is disabled. To change prescaler from the WDT to the Timer0 module use the sequence shown in Example 6-2.
CHANGING PRESCALER (WDTTIMER0)
;Clear WDT and ; prescaler ;Bank 1 ;Select TMR0, new ; prescale value ' and clock source ; ;Bank 0
STATUS, RP0 b'xxxx0xxx'
MOVWF BCF
OPTION STATUS, RP0
EXAMPLE 6-1:
BCF CLRF BSF CLRWDT MOVLW MOVWF BCF
CHANGING PRESCALER (TIMER0WDT)
;Bank 0 ;Clear TMR0 ; and Prescaler ;Bank 1 ;Clears WDT ;Select new ; prescale value ;Bank 0
STATUS, RP0 TMR0 STATUS, RP0 b'xxxx1xxx' OPTION STATUS, RP0
TABLE 6-1:
REGISTERS ASSOCIATED WITH TIMER0
Value on Power-on Reset xxxx xxxx INTE T0SE TRISA4 RBIE PSA TRISA3 T0IF PS2 TRISA2 INTF PS1 TRISA1 RBIF PS0 TRISA0 0000 000x 1111 1111 ---1 1111 Value on all other resets uuuu uuuu 0000 0000 1111 1111 ---1 1111
Address 01h 0Bh 81h 85h
Name TMR0 INTCON OPTION TRISA
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Timer0 module's register GIE RBPU -- EEIE INTEDG -- T0IE T0CS --
Legend: x = unknown, u = unchanged. - = unimplemented read as '0'. Shaded cells are not associated with Timer0.
(c) 1995 Microchip Technology Inc.
DS30081F-page 31
PIC16C8X
NOTES:
DS30081F-page 32
(c) 1995 Microchip Technology Inc.
PIC16C8X
7.0 DATA EEPROM MEMORY
The EEPROM data memory is readable and writable during normal operation (full VDD range). This memory is not directly mapped in the register file space. Instead it is indirectly addressed through the Special Function Registers. There are four SFRs used to read and write this memory. These registers are: * * * * EECON1 EECON2 EEDATA EEADR When the device is code protected, the CPU may continue to read and write the data EEPROM memory. The device programmer can no longer access this memory.
7.1
EEADR
The EEADR register can address up to a maximum of 256 bytes of data EEPROM. Only the first 64 bytes of data EEPROM are implemented and only six of the eight bits in the register (EEADR<5:0>) are required. The upper two bits are address decoded. This means that these two bits should always be '0' to ensure that the address is in the 64 byte memory space.
EEDATA holds the 8-bit data for read/write, and EEADR holds the address of the EEPROM location being accessed. PIC16C8X devices have 64 bytes of data EEPROM with an address range from 0h to 3Fh. The EEPROM data memory allows byte read and write. A byte write automatically erases the location and writes the new data (erase before write). The EEPROM data memory is rated for high erase/write cycles. The write time is controlled by an on-chip timer. The write-time will vary with voltage and temperature as well as from chip to chip. Please refer to AC specifications for exact limits.
FIGURE 7-1:
U -- bit7 U --
EECON1 REGISTER (ADDRESS 88h)
U -- R/W-0 EEIF R/W-x WRERR R/W-0 WREN R/S-0 WR R/S-x RD bit0 = Readable bit = Writable bit = Settable bit = Unimplemented bit, read as `0' - n = Value at POR reset R W S U
bit 7:5 bit 4
Unimplemented: Read as '0' EEIF: EEPROM Write Operation Interrupt Flag bit 1 = The write operation completed (must be cleared in software) 0 = The write operation is not complete or has not been started WRERR: EEPROM Error Flag bit 1 = A write operation is prematurely terminated (any MCLR reset or any WDT reset during normal operation) 0 = The write operation completed WREN: EEPROM Write Enable bit 1 = Allows write cycles 0 = Inhibits write to the data EEPROM WR: Write Control bit 1 = initiates a write cycle. (The bit is cleared by hardware once write is complete. The WR bit can only be set (not cleared) in software. 0 = Write cycle to the data EEPROM is complete RD: Read Control bit 1 = Initiates an EEPROM read (read takes one cycle. RD is cleared in hardware. The RD bit can only be set (not cleared) in software). 0 = Does not initiate an EEPROM read
bit 3
bit 2
bit 1
bit 0
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DS30081F-page 33
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7.2 EECON1 and EECON2 Registers 7.4 Writing to the EEPROM Data Memory
EECON1 is the control register with five low order bits physically implemented. The upper-three bits are non-existent and read as '0's. Control bits RD and WR initiate read and write, respectively. These bits cannot be cleared, only set, in software. They are cleared in hardware at completion of the read or write operation. The inability to clear the WR bit in software prevents the accidental, premature termination of a write operation. The WREN bit, when set, will allow a write operation. On power-up, the WREN bit is clear. The WRERR bit is set when a write operation is interrupted by a MCLR reset or a WDT time-out reset during normal operation. In these situations, following reset, the user can check the WRERR bit and rewrite the location. The data and address will be unchanged in the EEDATA and EEADR registers. Interrupt flag bit EEIF is set when write is complete. It must be cleared in software. EECON2 is not a physical register. Reading EECON2 will read all '0's. The EECON2 register is used exclusively in the Data EEPROM write sequence. To write an EEPROM data location, the user must first write the address to the EEADR register and the data to the EEDATA register. Then the user must follow a specific sequence to initiate the write for each byte.
EXAMPLE 7-2:
BSF BCF MOVLW MOVWF MOVLW MOVWF BSF BSF
DATA EEPROM WRITE
STATUS, RP0 INTCON, GIE 55h EECON2 AAh EECON2 EECON1,WR INTCON, GIE ; ; ; ; ; ; ; ; ; Bank 1 Disable INTs. Write 55h Write AAh Set WR bit begin write Enable INTs.
The write will not initiate if the above sequence is not exactly followed (write 55h to EECON2, write AAh to EECON2, then set WR bit) for each byte. We strongly recommend that interrupts be disabled during this code segment. Additionally, the WREN bit in EECON1 must be set to enable write. This mechanism prevents accidental writes to data EEPROM due to errant (unexpected) code execution (i.e., lost programs). The user should keep the WREN bit clear at all times, except when updating EEPROM. The WREN bit is not cleared by hardware After a write sequence has been initiated, clearing the WREN bit will not affect this write cycle. The WR bit will be inhibited from being set unless the WREN bit is set. At the completion of the write cycle, the WR bit is cleared in hardware and the EE Write Complete Interrupt Flag bit (EEIF) is set. The user can either enable this interrupt or poll this bit. EEIF must be cleared by software. Note: For the PIC16C84 Only; The data EEPROM memory E/W cycle time may occasionally exceed the 10 ms specification (typical). To ensure that the write cycle is complete, use the EE interrupt or poll the WR bit (EECON1<1>). Both these events signify the completion of the write cycle.
7.3
Reading the EEPROM Data Memory
To read a data memory location, the user must write the address to the EEADR register and then set control bit RD (EECON1<0>). The data is available, in the very next cycle, in the EEDATA register; therefore it can be read in the next instruction. EEDATA will hold this value until another read or until it is written to by the user (during a write operation).
EXAMPLE 7-1:
BCF MOVLW MOVWF BSF BSF BCF MOVF
DATA EEPROM READ
; ; ; ; ; ; ; Bank 0 Address to read Bank 1 EE Read Bank 0 W = EEDATA
STATUS, RP0 CONFIG_ADDR EEADR STATUS, RP0 EECON1, RD STATUS, RP0 EEDATA, W
Required Sequence
DS30081F-page 34
(c) 1995 Microchip Technology Inc.
PIC16C8X
7.5 Write Verify 7.6 Protection Against Spurious Write
Depending on the application, good programming practice may dictate that the value written to the Data EEPROM should be verified (Example 7-3) to the desired value to be written. This should be used in applications where an EEPROM bit will be stressed near the specification limit. The Total Endurance disk will help determine your comfort level. Generally the EEPROM write failure will be a bit which was written as a '1', but reads back as a '0' (due to leakage off the bit). There are conditions when the device may not want to write to the data EEPROM memory. To protect against spurious EEPROM writes, various mechanisms have been built in. On power-up, WREN is cleared. Also, the Power-up Timer (72 ms duration) prevents EEPROM write. The write initiate sequence and the WREN bit together help prevent an accidental write during brown-out, power glitch, or software malfunction.
7.7
EXAMPLE 7-3:
BCF : : MOVF BSF READ BSF
WRITE VERIFY
Bank 0 Any code can go here Must be in Bank 0 Bank 1
Data EEPROM Operation during Code Protect
STATUS, RP0 ; ; ; EEDATA, W ; STATUS, RP0 ; EECON1, RD
When the device is code protected, the CPU is able to read and write unscrambled data to the Data EEPROM. For ROM devices, there are two code protection bits (Section 8.9). One for the ROM program memory and one for the Data EEPROM memory.
BCF ; ; Is the value written (in W reg) and ; read (in EEDATA) the same? ; SUBWF EEDATA, W ; BTFSS STATUS, Z ; Is difference 0? GOTO WRITE_ERR ; NO, Write error : ; YES, Good write : ; Continue program
; YES, Read the ; value written STATUS, RP0 ; Bank 0
7.8
Note:
Power Consumption Considerations
For the PIC16C84 Only; It is recommended that the EEADR<7:6> bits be cleared. When either of these bits is set, the maximum IDD for the device is higher than when both are cleared. The specification is 400 A. With EEADR<7:6> cleared, the maximum is approximately 150 A.
TABLE 7-1:
Address Name
REGISTERS/BITS ASSOCIATED WITH DATA EEPROM
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on Power-on Reset xxxx xxxx xxxx xxxx EEIF WRERR WREN WR RD ---0 x000 ---- ---Value on all other resets uuuu uuuu uuuu uuuu ---0 q000 ---- ----
08h 09h 88h 89h
EEDATA EEADR EECON1 EECON2
EEPROM data register EEPROM address register -- -- --
EEPROM control register 2
Legend: x = unknown, u = unchanged, - = unimplemented read as '0', q = value depends upon condition. Shaded cells are not used by Data EEPROM.
(c) 1995 Microchip Technology Inc.
DS30081F-page 35
PIC16C8X
NOTES:
DS30081F-page 36
(c) 1995 Microchip Technology Inc.
PIC16C8X
8.0 SPECIAL FEATURES OF THE CPU
the chip in reset until the crystal oscillator is stable. The other is the Power-up Timer (PWRT), which provides a fixed delay of 72 ms (nominal) on power-up only. This design keeps the device in reset while the power supply stabilizes. With these two timers on-chip, most applications need no external reset circuitry. SLEEP mode offers a very low current power-down mode. The user can wake-up from SLEEP through external reset, Watchdog Timer time-out or through an interrupt. Several oscillator options are provided to allow the part to fit the application. The RC oscillator option saves system cost while the LP crystal option saves power. A set of configuration bits are used to select the various options.
What sets a microcontroller apart from other processors are special circuits to deal with the needs of real time applications. The PIC16C8X has a host of such features intended to maximize system reliability, minimize cost through elimination of external components, provide power saving operating modes and offer code protection. These features are: * OSC selection * Reset - Power-on Reset (POR) - Power-up Timer (PWRT) - Oscillator Start-up Timer (OST) * Interrupts * Watchdog Timer (WDT) * SLEEP * Code protection * ID locations * In-circuit serial programming The PIC16C8X has a Watchdog Timer which can be shut off only through configuration bits. It runs off its own RC oscillator for added reliability. There are two timers that offer necessary delays on power-up. One is the Oscillator Start-up Timer (OST), intended to keep
8.1
Configuration Bits
The configuration bits can be programmed (read as '0') or left unprogrammed (read as '1') to select various device configurations. These bits are mapped in program memory location 2007h. Address 2007h is beyond the user program memory space and it belongs to the special test/configuration memory space (2000h - 3FFFh). This space can only be accessed during programming.
FIGURE 8-1:
U-1 -- bit13 U-1 --
CONFIGURATION WORD - PIC16C84
U-1 -- U-1 -- U-1 -- U-1 -- U-1 -- U-1 -- U-1 -- R/P-u CP R/P-u R/P-u R/P-u R/P-u PWRTE WDTE FOSC1 FOSC0 bit0 R = Readable bit P = Programmable bit U = Unimplemented bit, read as `1' - n = Value at POR reset u = unchanged
bit 13:5 Unimplemented: Read as '1' bit 4 CP: Code Protection bit 1 = Code protection off 0 = All memory is code protected PWRTE: Power-up Timer Enable bit 1 = Power-up timer is enabled 0 = Power-up timer is disabled WDTE: Watchdog Timer Enable bit 1 = WDT enabled 0 = WDT disabled FOSC1:FOSC0: Oscillator Selection bits 11 = RC oscillator 10 = HS oscillator 01 = XT oscillator 00 = LP oscillator
bit 3
bit 2
bit 1:0
(c) 1995 Microchip Technology Inc.
DS30081F-page 37
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FIGURE 8-2:
R-u CP bit13 R-u CP
CONFIGURATION WORD - PIC16CR83 AND PIC16CR84
R-u CP R-u CP R-u CP R-u CP R/P-u DP R-u CP R-u CP R-u CP R-u R-u R-u R-u PWRTE WDTE FOSC1 FOSC0 bit0 R = Readable bit P = Programmable bit - n = Value at POR reset u = unchanged
bit 13:8 CP: Program Memory Code Protection bit 1 = Code protection off 0 = Program memory is code protected bit 7 DP: Data Memory Code Protection bit 1 = Code protection off 0 = Data memory is code protected CP: Program Memory Code Protection bit 1 = Code protection off 0 = Program memory is code protected PWRTE: Power-up Timer Enable bit 1 = Power-up timer is disabled 0 = Power-up timer is enabled WDTE: Watchdog Timer Enable bit 1 = WDT enabled 0 = WDT disabled FOSC1:FOSC0: Oscillator Selection bits 11 = RC oscillator 10 = HS oscillator 01 = XT oscillator 00 = LP oscillator
bit 6:4
bit 3
bit 2
bit 1:0
FIGURE 8-3:
CONFIGURATION WORD - PIC16C83 AND PIC16C84A
R/P-u CP R/P-u R/P-u R/P-u R/P-u PWRTE WDTE FOSC1 FOSC0 bit0 R = Readable bit P = Programmable bit - n = Value at POR reset u = unchanged
R/P-u R/P-u R/P-u R/P-u R/P-u R/P-u R/P-u R/P-u R/P-u CP CP CP CP CP CP CP CP CP bit13
bit 13:4 CP: Code Protection bit 1 = Code protection off 0 = Program memory is code protected bit 3 PWRTE: Power-up Timer Enable bit 1 = Power-up timer is disabled 0 = Power-up timer is enabled WDTE: Watchdog Timer Enable bit 1 = WDT enabled 0 = WDT disabled FOSC1:FOSC0: Oscillator Selection bits 11 = RC oscillator 10 = HS oscillator 01 = XT oscillator 00 = LP oscillator
bit 2
bit 1:0
DS30081F-page 38
(c) 1995 Microchip Technology Inc.
PIC16C8X
8.2
8.2.1
Oscillator Configurations
OSCILLATOR TYPES
TABLE 8-1:
PIC16C84 CAPACITOR SELECTION FOR CERAMIC RESONATORS
The PIC16C8X can be operated in four different oscillator modes. The user can program two configuration bits (FOSC1 and FOSC0) to select one of these four modes: * * * * LP XT HS RC Low Power Crystal Crystal/Resonator High Speed Crystal/Resonator Resistor/Capacitor CRYSTAL OSCILLATOR / CERAMIC RESONATORS
Ranges Tested: Mode XT Freq 455 kHz 2.0 MHz 4.0 MHz 8.0 MHz 10.0 MHz OSC1/C1 OSC2/C2
HS
Note :
47 - 100 pF 47 - 100 pF 15 - 33 pF 15 - 33 pF 15 - 33 pF 15 - 33 pF 15 - 33 pF 15 - 33 pF 15 - 33 pF 15 - 33 pF
8.2.2
In XT, LP or HS modes a crystal or ceramic resonator is connected to the OSC1/CLKIN and OSC2/CLKOUT pins to establish oscillation (Figure 8-4).
FIGURE 8-4:
CRYSTAL/CERAMIC RESONATOR OPERATION (HS, XT OR LP OSC CONFIGURATION)
OSC1
Recommended values of C1 and C2 are identical to the ranges tested table. Higher capacitance increases the stability of the oscillator but also increases the start-up time. These values are for design guidance only. Since each resonator has its own characteristics, the user should consult the resonator manufacturer for the appropriate values of external components.
Resonators Tested: 455 kHz 2.0 MHz 4.0 MHz 8.0 MHz 10.0 MHz Panasonic EFO-A455K04B Murata Erie CSA2.00MG Murata Erie CSA4.00MG Murata Erie CSA8.00MT Murata Erie CSA10.00MTZ 0.3% 0.5% 0.5% 0.5% 0.5%
C1 XTAL OSC2 C2 RS Note1 RF
To internal logic SLEEP
None of the resonators had built-in capacitors.
TABLE 8-2:
PIC16CXX
See Table 8-1 and Table 8-3 for recommended values of C1 and C2. Note 1: A series resistor may be required for AT strip cut crystals. Ranges Tested: Mode XT The PIC16C8X oscillator design requires the use of a parallel cut crystal. Use of a series cut crystal may give a frequency out of the crystal manufacturers specifications. When in XT, LP or HS modes, the device can have an external clock source to drive the OSC1/CLKIN pin (Figure 8-5).
PIC16C83/R83/84A/R84 CAPACITOR SELECTION FOR CERAMIC RESONATORS
Freq 455 kHz 2.0 MHz 4.0 MHz 8.0 MHz 10.0 MHz
OSC1/C1
OSC2/C2
HS
Note :
47 - 100 pF 47 - 100 pF 15 - 33 pF 15 - 33 pF 15 - 33 pF 15 - 33 pF 15 - 33 pF 15 - 33 pF 15 - 33 pF 15 - 33 pF
FIGURE 8-5:
EXTERNAL CLOCK INPUT OPERATION (HS, XT OR LP OSC CONFIGURATION)
OSC1 PIC16CXX Open OSC2
Recommended values of C1 and C2 are identical to the ranges tested table. Higher capacitance increases the stability of the oscillator but also increases the start-up time. These values are for design guidance only. Since each resonator has its own characteristics, the user should consult the resonator manufacturer for the appropriate values of external components.
Clock from ext. system
Resonators Tested: 455 kHz 2.0 MHz 4.0 MHz 8.0 MHz 10.0 MHz Panasonic EFO-A455K04B Murata Erie CSA2.00MG Murata Erie CSA4.00MG Murata Erie CSA8.00MT Murata Erie CSA10.00MTZ 0.3% 0.5% 0.5% 0.5% 0.5%
None of the resonators had built-in capacitors.
(c) 1995 Microchip Technology Inc.
DS30081F-page 39
PIC16C8X
TABLE 8-3: PIC16C84 CAPACITOR SELECTION FOR CRYSTAL OSCILLATOR
Freq 32 kHz 200 kHz 100 kHz 2 MHz 4 MHz 4 MHz 10 MHz OSC1/C1 OSC2/C2
TABLE 8-4:
PIC16C83/R83/84A/R84 CAPACITOR SELECTION FOR CRYSTAL OSCILLATOR
Freq OSC1/C1 68 - 100 pF 15 - 33 pF 100 - 150 pF 15 - 33 pF 15 - 33 pF 15 - 33 pF 15 - 33 pF OSC2/C2 68 - 100 pF 15 - 33 pF 100 - 150 pF 15 - 33 pF 15 - 33 pF 15 - 33 pF 15 - 33 pF
Mode LP XT
Mode LP XT
HS
Note :
68 - 100 pF 68 - 100 pF 15 - 33 pF 15 - 33 pF 100 - 150 pF 100 - 150 pF 15 - 33 pF 15 - 33 pF 15 - 33 pF 15 - 33 pF 15 - 33 pF 15 - 33 pF 15 - 33 pF 15 - 33 pF
HS
Note :
32 kHz 200 kHz 100 kHz 2 MHz 4 MHz 4 MHz 10 MHz
Higher capacitance increases the stability of oscillator but also increases the start-up time. These values are for design guidance only. Rs may be required in HS mode as well as XT mode to avoid overdriving crystals with low drive level specification. Since each crystal has its own characteristics, the user should consult the crystal manufacturer for appropriate values of external components. For VDD > 4.5V, C1 = C2 30 pF is recommended.
Higher capacitance increases the stability of oscillator but also increases the start-up time. These values are for design guidance only. Rs may be required in HS mode as well as XT mode to avoid overdriving crystals with low drive level specification. Since each crystal has its own characteristics, the user should consult the crystal manufacturer for appropriate values of external components. For VDD > 4.5V, C1 = C2 30 pF is recommended.
Crystals Tested: 32.768 kHz 100 kHz 200 kHz 1.0 MHz 2.0 MHz 4.0 MHz 10.0 MHz Epson C-001R32.768K-A Epson C-2 100.00 KC-P STD XTL 200.000 KHz ECS ECS-10-13-2 ECS ECS-20-S-2 ECS ECS-40-S-4 ECS ECS-100-S-4 20 PPM 20 PPM 20 PPM 50 PPM 50 PPM 50 PPM 50 PPM
Crystals Tested: 32.768 kHz 100 kHz 200 kHz 1.0 MHz 2.0 MHz 4.0 MHz 10.0 MHz Epson C-001R32.768K-A Epson C-2 100.00 KC-P STD XTL 200.000 KHz ECS ECS-10-13-2 ECS ECS-20-S-2 ECS ECS-40-S-4 ECS ECS-100-S-4 20 PPM 20 PPM 20 PPM 50 PPM 50 PPM 50 PPM 50 PPM
DS30081F-page 40
(c) 1995 Microchip Technology Inc.
PIC16C8X
8.2.3 EXTERNAL CRYSTAL OSCILLATOR CIRCUIT 8.2.4 RC OSCILLATOR For timing insensitive applications the RC device option offers additional cost savings. The RC oscillator frequency is a function of the supply voltage, the resistor (Rext) values, capacitor (Cext) values, and the operating temperature. In addition to this, the oscillator frequency will vary from unit to unit due to normal process parameter variation. Furthermore, the difference in lead frame capacitance between package types also affects the oscillation frequency, especially for low Cext values. The user needs to take into account variation due to tolerance of the external R and C components. Figure 8-8 shows how an R/C combination is connected to the PIC16C8X. For Rext values below 2.2 k, the oscillator operation may become unstable, or stop completely. For very high Rext values (e.g., 1 M), the oscillator becomes sensitive to noise, humidity and leakage. Thus, we recommend keeping Rext between 3 k and 100 k. Although the oscillator will operate with no external capacitor (Cext = 0 pF), we recommend using values above 20 pF for noise and stability reasons. With little or no external capacitance, the oscillation frequency can vary dramatically due to changes in external capacitances, such as PCB trace capacitance or package lead frame capacitance. See the electrical specification section for RC frequency variation from part to part due to normal process variation. The variation is larger for larger R (since leakage current variation will affect RC frequency more for large R) and for smaller C (since variation of input capacitance has a greater affect on RC frequency). See the electrical specification section for variation of oscillator frequency due to VDD for given Rext/Cext values as well as frequency variation due to operating temperature. The oscillator frequency, divided by 4, is available on the OSC2/CLKOUT pin, and can be used for test purposes or to synchronize other logic (see Figure 3-2 for waveform).
Either a prepackaged oscillator can be used or a simple oscillator circuit with TTL gates can be built. Prepackaged oscillators provide a wide operating range and better stability. A well-designed crystal oscillator will provide good performance with TTL gates. Two types of crystal oscillator circuits are available; one with series resonance, and one with parallel resonance. Figure 8-6 shows a parallel resonant oscillator circuit. The circuit is designed to use the fundamental frequency of the crystal. The 74AS04 inverter performs the 180-degree phase shift that a parallel oscillator requires. The 4.7 k resistor provides negative feedback for stability. The 10 k potentiometer biases the 74AS04 in the linear region. This could be used for external oscillator designs.
FIGURE 8-6:
EXTERNAL PARALLEL RESONANT CRYSTAL OSCILLATOR CIRCUIT
To Other Devices
+5V 10k 4.7k 74AS04 74AS04 CLKIN PIC16CXX
10k XTAL 10k 20 pF 20 pF
Figure 8-7 shows a series resonant oscillator circuit. This circuit is also designed to use the fundamental frequency of the crystal. The inverter performs a 180-degree phase shift. The 330 k resistors provide the negative feedback to bias the inverters in their linear region.
FIGURE 8-8:
VDD Rext
RC OSCILLATOR MODE
FIGURE 8-7:
EXTERNAL SERIES RESONANT CRYSTAL OSCILLATOR CIRCUIT
To Other Devices 74AS04 CLKIN
OSC1
330 k 74AS04 0.1 F XTAL 330 k 74AS04
Internal clock PIC16CXX
PIC16CXX
Cext VSS Fosc/4 OSC2/CLKOUT
Note:
When the device oscillator is in RC mode, do not drive the OSC1 pin with an external clock or you may damage the device.
(c) 1995 Microchip Technology Inc.
DS30081F-page 41
PIC16C8X
8.3 Reset 8.4
The PIC16C8X differentiates between various kinds of reset: * * * * * Power-on Reset (POR) MCLR reset during normal operation MCLR reset during SLEEP WDT Reset (during normal operation) WDT Wake-up (during SLEEP) 8.4.1
Power-on Reset (POR), Power-up Timer (PWRT) and Oscillator Start-up Timer (OST)
POWER-ON RESET (POR)
Some registers are not affected in any reset condition; their status is unknown on a POR reset and unchanged in any other reset. Most other registers are reset to a "reset state" on POR, MCLR or WDT reset during normal operation and on MCLR reset during SLEEP. They are not affected by a WDT reset during SLEEP, since this reset is viewed as the resumption of normal operation. The TO and PD bits are set or cleared differently in different reset situations (Table 8-6). These bits are used in software to determine the nature of the reset. Table 8-8 gives a full description of reset states for all registers. Figure 8-9 shows a simplified block diagram of the on-chip reset circuit. For all devices, except the PIC16C84, the MCLR reset path has a noise filter to ignore small pulses. The electrical specifications specifies the pulse width requirements for the MCLR pin.
A Power-on Reset pulse is generated on-chip when VDD rise is detected (in the range of 1.2V - 1.7V). To take advantage of the POR, just tie the MCLR pin directly (or through a resistor) to VDD. This will eliminate external RC components usually needed to create Power-on Reset. A minimum rise time for VDD must be met for this to operate properly. See Electrical Specifications for details. When the device starts normal operation (exits the reset condition), device operating parameters (voltage, frequency, temperature, ...) must be meet to ensure operation. If these conditions are not met, the device must be held in reset until the operating conditions are met. For additional information, refer to Application Note AN607, "Power-up Trouble Shooting." The POR circuit does not produce an internal reset when VDD declines.
FIGURE 8-9:
SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
External Reset
MCLR WDT Module VDD rise detect VDD OST/PWRT OST 10-bit Ripple counter OSC1/ CLKIN PWRT On-chip RC OSC(1) 10-bit Ripple counter R Q Chip_Reset SLEEP WDT Time_Out Reset Power_on_Reset S
Enable PWRT
Note 1: This is a separate oscillator from the RC oscillator of the CLKIN pin.
See Table 8-5
Enable OST
DS30081F-page 42
(c) 1995 Microchip Technology Inc.
PIC16C8X
8.4.2 POWER-UP TIMER (PWRT) 8.4.4 TIME-OUT SEQUENCE The Power-up Timer provides a fixed 72 ms nominal time-out on power-up only, from POR. The Power-up Timer operates on an internal RC oscillator. The chip is kept in reset as long as the PWRT is active. The PWRT delay allows the VDD to rise to an acceptable level. A configuration bit, PWRTE, can enable/disable the PWRT (see Figure 8-1, Figure 8-2, and Figure 8-3 for the operation of the PWRTE bit for a particular device). The power-up time delay will vary from chip to chip due to VDD, temperature, and process variation. See DC parameters for details. 8.4.3 OSCILLATOR START-UP TIMER (OST)
XT, HS, LP RC
On power-up (Figure 8-10, Figure 8-11, and Figure 8-12) the time-out sequence is as follows: First PWRT time-out is invoked after a POR has expired. Then the OST is activated. The total time-out will vary based on oscillator configuration and PWRTE configuration bit status. For example, in RC mode with the PWRT disabled, there will be no time-out at all.
TABLE 8-5:
Oscillator Configuration
TIME-OUT IN VARIOUS SITUATIONS
Power-up PWRT PWRT Enabled Disabled 72 ms + 1024TOSC 1024TOSC 72 ms -- Wake-up from SLEEP 1024TOSC --
The Oscillator Start-up Timer (OST) provides a 1024 oscillator cycle delay (from OSC1 input) after the PWRT delay ends. This ensures the crystal oscillator or resonator has started and stabilized. The OST time-out is invoked only for XT, LP and HS modes and only on Power-on Reset or wake-up from SLEEP.
Since the time-outs occur from the POR reset pulse, if MCLR is kept low long enough, the time-outs will expire. Then bringing MCLR high, execution will begin immediately (Figure 8-11). This is useful for testing purposes or to synchronize more than one PIC16CXX device when operating in parallel. Table 8-6 shows the significance of the TO and PD bits. Table 8-7 lists the reset conditions for some special registers, while Table 8-8 lists the reset conditions for all the registers.
TABLE 8-6:
TO 1 0 x 0 0 1 1 PD 1 x 0 1 0 1 0
STATUS BITS AND THEIR SIGNIFICANCE
Condition Power-on Reset Illegal, TO is set on POR Illegal, PD is set on POR WDT Reset (during normal operation) WDT Wake-up MCLR Reset during normal operation MCLR Reset during SLEEP or interrupt wake-up from SLEEP
TABLE 8-7:
RESET CONDITION FOR PROGRAM COUNTER AND THE STATUS REGISTER
Condition Program Counter 000h 000h 000h 000h PC + 1 PC + 1 (1) STATUS Register 0001 1xxx 0001 1uuu 0001 0uuu 0000 1uuu uuu0 0uuu uuu1 0uuu
Power-on Reset MCLR Reset during normal operation MCLR Reset during SLEEP WDT Reset (during normal operation) WDT Wake-up Interrupt wake-up from SLEEP
Legend: u = unchanged, x = unknown. Note 1: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h).
(c) 1995 Microchip Technology Inc.
DS30081F-page 43
PIC16C8X
TABLE 8-8: INITIALIZATION CONDITIONS FOR ALL REGISTERS
MCLR Reset during: - normal operation - SLEEP WDT Reset during normal operation uuuu uuuu ---- ---uuuu uuuu 0000h 000q quuu(3) uuuu uuuu ---u uuuu uuuu uuuu uuuu uuuu uuuu uuuu ---0 0000 0000 000u ---- ---1111 1111 0000h 000q quuu(3) uuuu uuuu ---1 1111 1111 1111 ---0 q000 ---- ------0 0000 0000 000u Wake-up from SLEEP: - through interrupt - through WDT time-out
Register
Address
Power-on Reset
W INDF TMR0 PCL STATUS FSR PORTA PORTB EEDATA EEADR PCLATH INTCON INDF OPTION PCL STATUS FSR TRISA TRISB EECON1 EECON2 PCLATH INTCON
-- 00h 01h 02h 03h 04h 05h 06h 08h 09h 0Ah 0Bh 80h 81h 82h 83h 84h 85h 86h 88h 89h 8Ah 8Bh
xxxx xxxx ---- ---xxxx xxxx 0000h 0001 1xxx xxxx xxxx ---x xxxx xxxx xxxx xxxx xxxx xxxx xxxx ---0 0000 0000 000x ---- ---1111 1111 0000h 0001 1xxx xxxx xxxx ---1 1111 1111 1111 ---0 x000 ---- ------0 0000 0000 000x
uuuu uuuu ---- ---uuuu uuuu PC + 1(2) uuuq quuu(3) uuuu uuuu ---u uuuu uuuu uuuu uuuu uuuu uuuu uuuu ---u uuuu uuuu uuuu(1) ---- ---uuuu uuuu PC + 1 uuuq quuu(3) uuuu uuuu ---u uuuu uuuu uuuu ---0 uuuu ---- ------u uuuu uuuu uuuu(1)
Legend: u = unchanged, x = unknown, - = unimplemented bit read as '0', q = value depends on condition. Note 1: One or more bits in INTCON will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h). 3: Table 8-7 lists the reset value for each specific condition.
DS30081F-page 44
(c) 1995 Microchip Technology Inc.
PIC16C8X
FIGURE 8-10: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1
VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
FIGURE 8-11: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2
VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
FIGURE 8-12: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD)
VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
(c) 1995 Microchip Technology Inc.
DS30081F-page 45
PIC16C8X
FIGURE 8-13: EXTERNAL POWER-ON RESET CIRCUIT (FOR SLOW VDD POWER-UP)
VDD D VDD
FIGURE 8-14: BROWN-OUT PROTECTION CIRCUIT 1
VDD VDD 33k 10k MCLR 40k PIC16CXX
R R1 MCLR C PIC16CXX
Note 1: External Power-on Reset circuit is required only if VDD power-up rate is too slow. The diode D helps discharge the capacitor quickly when VDD powers down. 2: R < 40 k is recommended to make sure that voltage drop across R does not exceed 0.2V (max leakage current spec on MCLR pin is 5 A). A larger voltage drop will degrade VIH level on the MCLR pin. 3: R1 = 100 to 1 k will limit any current flowing into MCLR from external capacitor C in the event of an MCLR pin breakdown due to ESD or EOS.
This circuit will activate reset when VDD goes below (Vz + 0.7V) where Vz = Zener voltage.
FIGURE 8-15: BROWN-OUT PROTECTION CIRCUIT 2
VDD VDD R1 Q1 MCLR R2 40k PIC16CXX
This brown-out circuit is less expensive, although less accurate. Transistor Q1 turns off when VDD is below a certain level such that:
VDD *
R1 R1 + R2
= 0.7V
DS30081F-page 46
(c) 1995 Microchip Technology Inc.
PIC16C8X
8.5 Interrupts
The PIC16C8X group has 4 sources of interrupt: * * * * External interrupt RB0/INT pin TMR0 overflow interrupt PORTB change interrupts (pins RB7:RB4) EEPROM write complete interrupt When an interrupt is responded to; the GIE bit is cleared to disable any further interrupt, the return address is pushed onto the stack and the PC is loaded with 0004h. For external interrupt events, such as the RB0/INT pin or PORTB change interrupt, the interrupt latency will be three to four instruction cycles. The exact latency depends when the interrupt event occurs (Figure 8-17). The latency is the same for both one and two cycle instructions. Once in the interrupt service routine the source(s) of the interrupt can be determined by polling the interrupt flag bits. The interrupt flag bit(s) must be cleared in software before re-enabling interrupts to avoid infinite interrupt requests.
The interrupt control register (INTCON) records individual interrupt requests in flag bits. It also contains the individual and global interrupt enable bits. The global interrupt enable bit, GIE (INTCON<7>) enables (if set) all un-masked interrupts or disables (if cleared) all interrupts. Individual interrupts can be disabled through their corresponding enable bits in INTCON register. Bit GIE is cleared on reset. The "return from interrupt" instruction, RETFIE, exits interrupt routine as well as sets the GIE bit, which re-enable interrupts. The RB0/INT pin interrupt, the RB port change interrupt and the TMR0 overflow interrupt flags are contained in the INTCON register.
Note 1: Individual interrupt flag bits are set regardless of the status of their corresponding mask bit or the GIE bit. Note 2: For the PIC16C84 Only; If an interrupt occurs while the Global Interrupt Enable (GIE) bit is being cleared, the GIE bit may unintentionally be re-enabled by the user's Interrupt Service Routine (the RETFIE instruction). The events that would cause this to occur are: 1. 2. An instruction clears the GIE bit while an interrupt is acknowledged The program branches to the Interrupt vector and executes the Interrupt Service Routine. The Interrupt Service Routine completes with the execution of the RETFIE instruction. This causes the GIE bit to be set (enables interrupts), and the program returns to the instruction after the one which was meant to disable interrupts.
3.
The method to ensure that interrupts are globally disabled is: 1. Ensure that the GIE bit is cleared by the instruction, as shown in the following code:
INTCON,GIE
LOOP
;Disable All ; Interrupts BTFSC INTCON,GIE ;All Interrupts ; Disabled? GOTO LOOP ;NO, try again ; Yes, continue ; with program ; flow
BCF
(c) 1995 Microchip Technology Inc.
DS30081F-page 47
PIC16C8X
FIGURE 8-16: INTERRUPT LOGIC
T0IF T0IE INTF INTE RBIF RBIE EEIF EEIE GIE
Wake-up (If in SLEEP mode)
Interrupt to CPU
FIGURE 8-17: INT PIN INTERRUPT TIMING
Q1 OSC1 CLKOUT 3 INT pin INTF flag (INTCON<1>) GIE bit (INTCON<7>) INSTRUCTION FLOW PC Instruction fetched Instruction executed PC Inst (PC) Inst (PC-1) PC+1 Inst (PC+1) Inst (PC) PC+1 -- Dummy Cycle 0004h Inst (0004h) Dummy Cycle 0005h Inst (0005h) Inst (0004h) 1 5 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
4 1 Interrupt Latency 2
Note 1: INTF flag is sampled here (every Q1). 2: Interrupt latency = 3-4Tcy where Tcy = instruction cycle time. Latency is the same whether Inst (PC) is a single cycle or a 2-cycle instruction. 3: CLKOUT is available only in RC oscillator mode. 4: For minimum width of INT pulse, refer to AC specs. 5: INTF is enabled to be set anytime during the Q4-Q1 cycles.
DS30081F-page 48
(c) 1995 Microchip Technology Inc.
PIC16C8X
8.5.1 INT INTERRUPT
8.6
Context Saving During Interrupts
External interrupt on RB0/INT pin is edge triggered: either rising if INTEDG bit (OPTION<6>) is set, or falling, if INTEDG bit is clear. When a valid edge appears on the RB0/INT pin, the INTF bit (INTCON<1>) is set. This interrupt can be disabled by clearing control bit INTE (INTCON<4>). Flag bit INTF must be cleared in software via the interrupt service routine before re-enabling this interrupt. The INT interrupt can wake the processor from SLEEP (Section 8.8) only if the INTE bit was set prior to going into SLEEP. The status of the GIE bit decides whether the processor branches to the interrupt vector following wake-up. 8.5.2 TMR0 INTERRUPT
During an interrupt, only the return PC value is saved on the stack. Typically, users wish to save key register values during an interrupt (e.g., W register and STATUS register). This is implemented in software. Example 8-1 stores and restores the STATUS and W register's values. The User defined registers, W_TEMP and STATUS_TEMP are the temporary storage locations for the W and STATUS registers values. Example 8-1 does the following: a) b) c) d) e) Stores the W register. Stores the STATUS register in STATUS_TEMP. Executes the Interrupt Service Routine code. Restores the STATUS (and bank select bit) register. Restores the W register.
An overflow (FFh 00h) in TMR0 will set flag bit T0IF (INTCON<2>). The interrupt can be enabled/disabled by setting/clearing enable bit T0IE (INTCON<5>) (Section 6.0). 8.5.3 PORT RB INTERRUPT
An input change on PORTB<7:4> sets flag bit RBIF (INTCON<0>). The interrupt can be enabled/disabled by setting/clearing enable bit RBIE (INTCON<3>) (Section 5.2). Note 1: For the PIC16C84 Only; If a change on an I/O pin should occur when a read operation of PORTB is being executed (start of the Q2 cycle), the RBIF interrupt flag bit may not get set. Note 2: For all other PIC16C8X devices; For a change on the I/O pin to be recognized, the pulse width must be at least TCY wide.
EXAMPLE 8-1:
PUSH MOVWF SWAPF MOVWF : : : : SWAPF MOVWF SWAPF SWAPF
SAVING STATUS AND W REGISTERS IN RAM
W_TEMP STATUS, W STATUS_TEMP ; ; ; : ; ; ; ; ; ; ; ; ; Copy W to TEMP register, Swap status to be saved into W Save status to STATUS_TEMP register Interrupt Service Routine should configure Bank as required Swap nibbles in STATUS_TEMP register and place result into W Move W into STATUS register (sets bank to original state) Swap nibbles in W_TEMP and place result in W_TEMP Swap nibbles in W_TEMP and place result into W
ISR
POP
STATUS_TEMP, W STATUS W_TEMP, F W_TEMP, W
(c) 1995 Microchip Technology Inc.
DS30081F-page 49
PIC16C8X
8.7 Watchdog Timer (WDT)
The Watchdog Timer is a free running on-chip RC oscillator which does not require any external components. This RC oscillator is separate from the RC oscillator of the OSC1/CLKIN pin. That means that the WDT will run even if the clock on the OSC1/CLKIN and OSC2/CLKOUT pins of the device has been stopped, for example, by execution of a SLEEP instruction. During normal operation a WDT time-out generates a device RESET. If the device is in SLEEP mode, a WDT Wake-up causes the device to wake-up and continue with normal operation. The WDT can be permanently disabled by programming configuration bit WDTE as a '0' (Section 8.1). 8.7.1 WDT PERIOD part (see DC specs). If longer time-out periods are desired, a prescaler with a division ratio of up to 1:128 can be assigned to the WDT under software control by writing to the OPTION register. Thus, time-out periods up to 2.3 seconds can be realized. The CLRWDT and SLEEP instructions clear the WDT and the postscaler (if assigned to the WDT) and prevent it from timing out and generating a device RESET condition. The TO bit in the STATUS register will be cleared upon a WDT time-out. 8.7.2 WDT PROGRAMMING CONSIDERATIONS
The WDT has a nominal time-out period of 18 ms, (with no prescaler). The time-out periods vary with temperature, VDD and process variations from part to
It should also be taken into account that under worst case conditions (VDD = Min., Temperature = Max., max. WDT prescaler) it may take several seconds before a WDT time-out occurs.
FIGURE 8-18: WATCHDOG TIMER BLOCK DIAGRAM
From TMR0 Clock Source (Figure 6-6)
0 WDT Timer
*
1
M U X
Postscaler 8 8 - to -1 MUX PS2:PS0
WDT Enable Bit
PSA
*
0 MUX 1
To TMR0 (Figure 6-6)
PSA
WDT Time-out
Note: PSA and PS2:PS0 are bits in the OPTION register.
TABLE 8-9:
Address Name
SUMMARY OF REGISTERS ASSOCIATED WITH THE WATCHDOG TIMER
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 PWRTE(1) PSA Bit 2 Bit 1 Bit 0 Value on Power-on Reset (2) 1111 1111 1111 1111 Value on all other resets
2007h 81h
Config. bits OPTION
(2) RBPU
(2) INTEDG
(2) T0CS
CP T0SE
WDTE PS2
FOSC1 PS1
FOSC0 PS0
Legend: x = unknown. Shaded cells are not used by the WDT. Note 1: See Figure 8-1, Figure 8-2, and Figure 8-3 for operation of the PWRTE bit. 2: See Figure 8-1, Figure 8-2, Figure 8-3, and Section 8.9 for operation of the Code and Data protection bits.
DS30081F-page 50
(c) 1995 Microchip Technology Inc.
PIC16C8X
8.8 Power-down Mode (SLEEP)
Peripherals cannot generate interrupts during SLEEP, since no on-chip Q clocks are present. The first event (MCLR reset) will cause a device reset. The two latter events are considered a continuation of program execution. The TO and PD bits can be used to determine the cause of a device reset. The PD bit, which is set on power-up, is cleared when SLEEP is invoked. The TO bit is cleared if a WDT time-out occurred (and caused wake-up). While the SLEEP instruction is being executed, the next instruction (PC + 1) is pre-fetched. For the device to wake-up through an interrupt event, the corresponding interrupt enable bit must be set (enabled). Wake-up occurs regardless of the state of the GIE bit. If the GIE bit is clear (disabled), the device continues execution at the instruction after the SLEEP instruction. If the GIE bit is set (enabled), the device executes the instruction after the SLEEP instruction and then branches to the interrupt address (0004h). In cases where the execution of the instruction following SLEEP is not desirable, the user should have a NOP after the SLEEP instruction. Note: If global interrupts are disabled (GIE cleared), but any interrupt source has both its interrupt enable bit and corresponding interrupt flag bits set, the device will immediately wake from sleep. The SLEEP instruction is completely executed. The Power-down mode is entered by executing the SLEEP instruction. If enabled, the Watchdog Timer will be cleared but keeps running, the PD bit (STATUS<3>) is cleared, the TO bit (STATUS<4>) is set, and the oscillator driver is turned off. The I/O ports maintain the status they had, before the SLEEP instruction was executed (driving high, low, or hi-impedance). For the lowest current consumption, in SLEEP mode, place all I/O pins at either at VDD, or VSS, with no external circuitry drawing current from the I/O pin, and disable external clocks. I/O pins that are hi-impedance inputs should be pulled high or low externally to avoid switching currents caused by floating inputs. The T0CKI input should also be at VDD or VSS. The contribution from on-chip pull-ups on PORTB should be considered. The MCLR pin must be at a logic high level (VIHMC). It should be noted that a RESET generated by a WDT time-out does not drive the MCLR pin low. 8.8.1 WAKE-UP FROM SLEEP
The device can wake-up from SLEEP through one of the following events: 1. 2. 3. External reset input on MCLR pin. WDT Wake-up (if WDT was enabled). Interrupt from RB0/INT pin, RB port change, or data EEPROM write complete.
The WDT is cleared when the device wakes-up from sleep, regardless of the source of wake-up.
FIGURE 8-19: WAKE-UP FROM SLEEP THROUGH INTERRUPT
Q1 OSC1 (1) tost(2) CLKOUT(4) INT pin INTF flag (INTCON<1>) GIE bit (INTCON<7>) INSTRUCTION FLOW PC Instruction fetched Instruction executed PC Inst (PC) = SLEEP Inst (PC-1) PC+1 Inst (PC+1) SLEEP Interrupt Latency (2) Processor in SLEEP PC+2 0004h (3) Inst (PC+2) Inst (PC+1) Dummy Cycle 0005h Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Note 1: XT or LP oscillator mode assumed. 2: Tost = 1024Tosc (drawing not to scale). This delay will not be there for RC osc mode. 3: When GIE is set, processor jumps to interrupt routine after wake-up. If GIE is clear, execution will continue in-line. 4: CLKOUT is not available in these osc modes, but shown here for timing reference.
(c) 1995 Microchip Technology Inc.
DS30081F-page 51
PIC16C8X
8.9 Code Protection 8.11 In-Circuit Serial Programming
The code in the program memory and data EEPROM memory can be protected by programming the code protect bit (Figure 8-1, Figure 8-2, and Figure 8-3). 8.9.1 ROM DEVICES PIC16C8X microcontrollers can be serially programmed while in the end application circuit. This is simply done with two lines for clock and data, and three other lines for power, ground, and the programming voltage. Customers can manufacture boards with unprogrammed devices, and then program the microcontroller just before shipping the product, allowing the most recent firmware or custom firmware to be programmed. The device is placed into a program/verify mode by holding the RB6 and RB7 pins low, while raising the MCLR pin from VIL to VIHH (see programming specification). RB6 becomes the programming clock and RB7 becomes the programming data. Both RB6 and RB7 are Schmitt Trigger inputs in this mode. After reset, to place the device into programming/verify mode, the program counter (PC) points to location 00h. A 6-bit command is then supplied to the device, 14-bits of program data is then supplied to or from the device, using load or read-type instructions. For complete details of serial programming, please refer to the PIC16CXX Programming Specifications (Literature #DS30189).
There are two protection configuration bits. One for the program memory, which is specified as part of the ROM code submittal. The second for the EEPROM data memory. When ROM devices complete testing, the EEPROM data memory code protect configuration bit will be programmed to the same state as the program memory code protect configuration bit. In applications where the device is code protected and the data EEPROM needs to be programmed before being placed in the application, the data EEPROM memory array needs to be erased and then the data memory code protect disabled. This will allow the desired data to be programmed into the device. The sequence to disable the data EEPROM memory protection is shown in the PIC16C84 Programming Specification (Literature number DS30189D) in Section 3.1.1. After programming the data EEPROM memory array, the data EEPROM memory code protect configuration bit should be programmed as desired.
8.10
ID Locations
FIGURE 8-20: TYPICAL IN-SYSTEM SERIAL PROGRAMMING CONNECTION
To Normal Connections PIC16CXX VDD VSS MCLR RB6 RB7
Four memory locations (2000h - 2003h) are designated as ID locations to store checksum or other code identification numbers. These locations are not accessible during normal execution but are readable and writable only during program/verify. Only the 4 least significant bits of ID location are usable. For ROM devices, these values are submitted along with the ROM code.
External Connector Signals +5V 0V VPP CLK Data I/O
To Normal Connections
For ROM devices, both the program memory and Data EEPROM memory may be read, but only the Data EEPROM memory may be programmed.
DS30081F-page 52
(c) 1995 Microchip Technology Inc.
PIC16C8X
9.0 INSTRUCTION SET SUMMARY
Each PIC16CXX instruction is a 14-bit word divided into an OPCODE which specifies the instruction type and one or more operands which further specify the operation of the instruction. The PIC16CXX instruction set summary in Table 9-2 lists byte-oriented, bit-oriented, and literal and control operations. Table 9-1 shows the opcode field descriptions. Byte-oriented instructions: 'f' represents a file register designator and 'd' represents a destination designator. The file register designator specifies which file register is to be used by the instruction. The destination designator specifies where the result of the operation is to be placed. If 'd' is 0, the result is placed in the W register. If 'd' is 1, the result is placed in the file register specified by the instruction. Bit-oriented instructions: 'b' represents a bit field designator which selects the number of the bit affected by the operation, while 'f' represents the address of the file in which the bit is located. Literal and control operations: 'k' represents an eight or eleven bit constant or literal value. The instruction set is highly orthogonal and is grouped into three basic categories: * Byte-oriented * Bit-oriented * Literal and control All instructions are executed within a single instruction cycle, unless a conditional test is true or the program counter is changed as a result of the instruction. The execution takes two instruction cycles with the second cycle executed as a NOP. Each cycle consists of four oscillator periods. Thus, for an oscillator frequency of 4 MHz, the normal instruction execution time is 1 s. The instruction execution time is 2 s for program branches. Table 9-2 lists the instructions Microchip's assembler (MPASM). recognized by
Figure 9-1 shows the three general formats of instructions. Note: To maintain upward compatibility with future PIC16CXX products, do not use the OPTION and TRIS instructions.
TABLE 9-1:
Field
f W b k x
OPCODE FIELD DESCRIPTIONS
Description
All examples use the following format to represent a hexadecimal number: 0xhh where h signifies a hexadecimal digit.
Register file address (0x00 to 0x7F) Working register (accumulator) Bit address within an 8-bit file register Literal field, constant data or label Don't care location (= 0 or 1) The assembler will generate code with x = 0. It is the recommended form of use for compatibility with all Microchip software tools. Destination select; d = 0: store result in W, d = 1: store result in file register f. Default is d = 1 Top of Stack Program Counter Global Interrupt Enable bit Watchdog Timer/Counter Time-out bit Power-down bit
FIGURE 9-1:
GENERAL FORMAT FOR INSTRUCTIONS
0
Byte-oriented file register operations 13 876 OPCODE d f (FILE #) d = 0 for destination W d = 1 for destination f f = 7-bit file register address Bit-oriented file register operations 13 10 9 76 OPCODE b (BIT #) f (FILE #) b = 3-bit bit address f = 7-bit file register address Literal and control operations General 13 OPCODE k = 8-bit immediate value CALL and GOTO instructions only 13 11 OPCODE 10 k (literal) 8 7 k (literal)
d
label Label name TOS PC GIE WDT TO PD
0
PCLATH Program Counter High Latch
0
dest Destination (Either the W register or the specified register file location) [] Options Contents Assigned to Register bit field In the set of
() <>
0
k = 11-bit immediate value
italics User defined term (font is courier)
(c) 1995 Microchip Technology Inc.
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TABLE 9-2:
Mnemonic, Operands ADDWF ANDWF CLRF CLRW COMF DECF DECFSZ INCF INCFSZ IORWF MOVF MOVWF NOP RLF RRF SUBWF SWAPF XORWF f, d f, d f f, d f, d f, d f, d f, d f, d f, d f f, d f, d f, d f, d f, d
INSTRUCTION SET SUMMARY
Description Cycles MSb Add W and f AND W with f Clear f Clear W Complement f Decrement f Decrement f, Skip if 0 Increment f Increment f, Skip if 0 Inclusive OR W with f Move f Move W to f No Operation Rotate left f through carry Rotate right f through carry Subtract W from f Swap nibbles in f Exclusive OR W with f 1 1 1 1 1 1 1(2) 1 1(2) 1 1 1 1 1 1 1 1 1 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0111 0101 0001 0001 1001 0011 1011 1010 1111 0100 1000 0000 0000 1101 1100 0010 1110 0110 dfff dfff lfff 0xxx dfff dfff dfff dfff dfff dfff dfff lfff 0xx0 dfff dfff dfff dfff dfff 14-Bit Opcode LSb ffff ffff ffff xxxx ffff ffff ffff ffff ffff ffff ffff ffff 0000 ffff ffff ffff ffff ffff Status Affected C,DC,Z Z Z Z Z Z None Z None Z Z None None C C C,DC,Z None Z Notes
1,2 1,2 2 1,2 1,2 1,2,3 1,2 1,2,3 1,2 1,2
1,2 1,2 1,2 1,2 1,2
BIT-ORIENTED FILE REGISTER OPERATIONS
BCF BSF BTFSC BTFSS f, b f, b f, b f, b Bit Clear f Bit Set f Bit Test f, Skip if Clear Bit Test f, Skip if Set 1 1 1 (2) 1 (2) 01 01 01 01 00bb 01bb 10bb 11bb bfff bfff bfff bfff ffff ffff ffff ffff None None None None 1,2 1,2 3 3
LITERAL AND CONTROL OPERATIONS ADDLW ANDLW CALL CLRWDT GOTO IORLW MOVLW RETFIE RETLW RETURN SLEEP SUBLW XORLW k k k k k k k k k Add literal and W AND literal with W Call subroutine Clear Watchdog Timer Go to address Inclusive OR literal with W Move literal to W Return from interrupt Return with literal in W Return from subroutine Go into standby mode Subtract W from literal Exclusive OR literal with W 1 1 2 1 2 1 1 2 2 2 1 1 1 11 11 10 00 10 11 11 00 11 00 00 11 11 111x 1001 0kkk 0000 1kkk 1000 00xx 0000 01xx 0000 0000 110x 1010 kkkk kkkk kkkk 0110 kkkk kkkk kkkk 0000 kkkk 0000 0110 kkkk kkkk kkkk kkkk kkkk 0100 kkkk kkkk kkkk 1001 kkkk 1000 0011 kkkk kkkk C,DC,Z Z TO,PD None Z None None None None TO,PD C,DC,Z Z
Note 1: When an I/O register is modified as a function of itself (i.e., MOVF PORTB, 1), the value used will be that value present on the pins themselves. For example, if the data latch is '1' for a pin configured as input and is driven low by an external device, the data will be written back with a '0'. 2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if assigned to the TMR0. 3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP.
DS30081F-page 54
(c) 1995 Microchip Technology Inc.
PIC16C8X
9.1
ADDLW Syntax: Operands: Operation: Status Affected: Encoding: Description:
Instruction Descriptions
Add Literal and W [ label ] ADDLW 0 k 255 (W) + k (W) C, DC, Z
11 111x kkkk kkkk The contents of the W register are added to the eight bit literal 'k' and the result is placed back in the W register.
ANDLW k Syntax: Operands: Operation: Status Affected: Encoding: Description:
AND Literal with W [ label ] ANDLW 0 k 255 (W) .AND. (k) (W) Z
11 1001 kkkk kkkk The contents of W register is AND'ed with the eight bit literal 'k'. The result is placed back in the W register.
k
Words: Cycles: Example
1 1
ADDLW 0x15 W W = = 0x10 0x25
Words: Cycles: Example
1 1
ANDLW W W 0x5F = = 0xA3 0x03
Before Instruction After Instruction
Before Instruction After Instruction
ADDWF Syntax: Operands: Operation: Status Affected: Encoding: Description:
Add W and f [ label ] ADDWF 0 f 127 d [0,1] (W) + (f) (dest) C, DC, Z
00 0111 dfff ffff Add the contents of the W register to register 'f'. If 'd' is 0 the result is stored in the W register. If 'd' is 1 the result is stored back in register 'f'.
ANDWF f,d Syntax: Operands: Operation: Status Affected: Encoding: Description:
AND W with f [ label ] ANDWF 0 f 127 d [0,1] (W) .AND. (f) (dest) Z
00 0101 dfff ffff AND the W register with register 'f'. If 'd' is 0 the result is stored in the W register. If 'd' is 1 the result is stored back in register 'f'.
f,d
Words: Cycles: Example
1 1
ADDWF FSR, 0 W= FSR = 0x17 0xC2 0xD9 0xC2
Words: Cycles: Example
1 1
ANDWF FSR, 1 W= FSR = 0x17 0xC2 0x17 0x02
Before Instruction
Before Instruction
After Instruction
W= FSR =
After Instruction
W= FSR =
(c) 1995 Microchip Technology Inc.
DS30081F-page 55
PIC16C8X
BCF Syntax: Operands: Operation: Status Affected: Encoding: Description: Words: Cycles: Example 1 1
BCF FLAG_REG, 7 FLAG_REG = 0xC7
Bit Clear f [ label ] BCF 0 f 127 0b7 0 (f) None
01 00bb bfff ffff Bit 'b' in register 'f' is cleared.
BTFSC f,b Syntax: Operands: Operation: Status Affected: Encoding: Description:
Bit Test f, Skip if Clear [ label ] BTFSC f,b 0 f 127 0b7 skip if (f) = 0 None
01 10bb bfff ffff If bit 'b' in register 'f' is 0 then the next instruction is skipped. If bit 'b' is 0 then the next instruction fetched during the current instruction execution is discarded, and a NOP is executed instead, making this a 2 cycle instruction.
Before Instruction After Instruction
FLAG_REG = 0x47
Words: Cycles: Example
1 1(2)
HERE FALSE TRUE BTFSC GOTO * * * PC = FLAG,1 PROCESS_CODE
Before Instruction
address HERE
After Instruction
if FLAG<1>=0, PC=address if FLAG<1>=1, PC=address TRUE FALSE
BSF Syntax: Operands: Operation: Status Affected: Encoding: Description: Words: Cycles: Example
Bit Set f [ label ] BSF 0 f 127 0b7 1 (f) None
01 01bb bfff ffff Bit 'b' in register 'f' is set.
f,b
1 1
BSF FLAG_REG, 7
Before Instruction
FLAG_REG= 0x0A
After Instruction
FLAG_REG= 0x8A
DS30081F-page 56
(c) 1995 Microchip Technology Inc.
PIC16C8X
BTFSS Syntax: Operands: Operation: Status Affected: Encoding: Description: Bit Test f, skip if Set [ label ] BTFSS f,b 0 f 127 0b<7 skip if (f) = 1 None
01 11bb bfff ffff If bit 'b' in register 'f' is 1 then the next instruction is skipped. If bit 'b' is 1, then the next instruction fetched during the current instruction execution, is discarded and a NOP is executed instead, making this a 2 cycle instruction.
CLRF Syntax: Operands: Operation: Status Affected: Encoding: Description: Words: Cycles: Example
Clear f [ label ] CLRF 0 f 127 00h (f) 1Z Z
00 0001 1fff ffff The contents of register 'f' are cleared and the Z bit is set.
f
1 1
CLRF FLAG_REG FLAG_REG = = = 0x5A 0x00 1
Words: Cycles: Example
1 1(2)
HERE FALSE TRUE BTFSC GOTO * * * PC = FLAG,1 PROCESS_CODE
Before Instruction After Instruction
FLAG_REG Z
Before Instruction
address HERE
After Instruction
if FLAG<1>=0, PC=address if FLAG<1>=1, PC=address FALSE TRUE
CALL Syntax: Operands: Operation:
Subroutine Call [ label ] CALL k 0 k 2047 (PC)+ 1 TOS, k (PC<10:0>), (PCLATH<4:3>) (PC<12:11>) None
10 0kkk kkkk kkkk Subroutine call. First, return address (PC+1) is pushed onto the stack. The eleven bit immediate address is loaded into PC bits <10:0>. The upper bits of the PC are loaded from PCLATH. CALL is a two cycle instruction.
CLRW Syntax: Operands: Operation: Status Affected: Encoding: Description: Words: Cycles: Example
Clear W Register [ label ] CLRW None 00h (W) 1Z Z
00 0001 0xxx xxxx W register is cleared. Zero bit (Z) is set.
Status Affected: Encoding: Description:
1 1
CLRW
Words: Cycles: Example
1 2
HERE CALL PC = THERE Address HERE Address THERE Address HERE
Before Instruction
W W Z = = = 0x5A 0x00 1
After Instruction
Before Instruction After Instruction
PC = TOS =
(c) 1995 Microchip Technology Inc.
DS30081F-page 57
PIC16C8X
CLRWDT Syntax: Operands: Operation: Clear Watchdog Timer [ label ] CLRWDT None 00h WDT 0 WDT prescaler, 1 TO 1 PD TO, PD
00 0000 0110 0100 The CLRWDT instruction resets the watchdog timer. It also resets the prescaler of the WDT. Status bits TO and PD are set.
DECF Syntax: Operands: Operation: Status Affected: Encoding: Description:
Decrement f [ label ] DECF f,d 0 f 127 d [0,1] (f) - 1 (dest) Z
00 0011 dfff ffff Decrement register 'f'. If 'd' is 0 the result is stored in the W register. If 'd' is 1 the result is stored back in register 'f'.
Status Affected: Encoding: Description:
Words: Cycles: Example
1 1
DECF CNT, 1 CNT Z = = = = 0x01 0 0x00 1
Words: Cycles: Example
1 1
CLRWDT
Before Instruction
Before Instruction
WDT counter = ? 0x00 0 1 1
After Instruction
CNT Z
After Instruction
WDT counter = WDT prescale = TO = PD =
COMF Syntax: Operands: Operation: Status Affected: Encoding: Description:
Complement f [ label ] COMF 0 f 127 d [0,1] ( f ) (dest) Z
00 1001 dfff ffff The contents of register 'f' are complemented. If 'd' is 0 the result is stored in W. If 'd' is 1 the result is stored back in register 'f'.
DECFSZ f,d Syntax: Operands: Operation: Status Affected: Encoding: Description:
Decrement f, Skip if 0 [ label ] DECFSZ f,d 0 f 127 d [0,1] (f) - 1 (dest); skip if result = 0 None
00 1011 dfff ffff
The contents of register 'f' are decremented. If 'd' is 0 the result is placed in the W register. If 'd' is 1 the result is placed back in register 'f'. If the result is 0, the next instruction, which is already fetched, is discarded. A NOP is executed instead making it a two cycle instruction.
Words: Cycles: Example
1 1
COMF REG1,0 REG1 = = = 0x13 0x13 0xEC
Words: Cycles: Example
1 1(2)
HERE DECFSZ GOTO CONTINUE * * * CNT, 1 LOOP
Before Instruction After Instruction
REG1 W
Before Instruction
PC CNT if CNT PC if CNT PC = = = = = addressHERE CNT - 1 0, address CONTINUE 0, address HERE+1
After Instruction
DS30081F-page 58
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PIC16C8X
GOTO Syntax: Operands: Operation: Status Affected: Encoding: Description: Go to address [ label ] GOTO k 0 k 2047 k (PC<10:0>) (PCLATH<4:3>) (PC<12:11>) None
10 1kkk kkkk kkkk GOTO is an unconditional branch. The eleven bit immediate value is loaded into PC bits <10:0>. The upper bits of PC are loaded from PCLATH<4:3>. GOTO is a two cycle instruction.
INCFSZ Syntax: Operands: Operation: Status Affected: Encoding: Description:
Increment f, Skip if 0 [ label ] INCFSZ f,d 0 f 127 d [0,1] (f) + 1 (dest), skip if result = 0 None
00 1111 dfff ffff The contents of register 'f' are incremented. If 'd' is 0 the result is placed in the W register. If 'd' is 1 the result is placed back in register 'f'. If the result is 0, the next instruction, which is already fetched, is discarded. A NOP is executed instead making it a two cycle instruction.
Words: Cycles: Example
1 2
GOTO THERE
Words: Cycles:
Address THERE
1 1(2)
HERE 1 INCFSZ CNT, LOOP
After Instruction
PC =
Example
GOTO CONTINUE * * *
Before Instruction
PC = addressHERE CNT + 1 0, addressCONTINUE 0, addressHERE +1
After Instruction
CNT = if CNT = PC = if CNT PC =
INCF Syntax: Operands: Operation: Status Affected: Encoding: Description:
Increment f [ label ] INCF f,d 0 f 127 d [0,1] (f) + 1 (dest) Z
00 1010 dfff ffff The contents of register 'f' are incremented. If 'd' is 0 the result is placed in the W register. If 'd' is 1 the result is placed back in register 'f'.
IORLW Syntax: Operands: Operation: Status Affected: Encoding: Description:
Inclusive OR Literal with W [ label ] IORLW k 0 k 255 (W) .OR. (k) (W) Z
11 1000 kkkk kkkk The contents of the W register are OR'ed to the eight bit literal 'k'. The result is placed in the W register.
Words: Cycles: Example
1 1
IORLW W 0x35 = = 0x9A 0xBF
Words: Cycles: Example
1 1
INCF CNT, 1 CNT Z = = = = 0xFF 0 0x00 1
Before Instruction After Instruction
W
Before Instruction
After Instruction
CNT Z
(c) 1995 Microchip Technology Inc.
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PIC16C8X
IORWF Syntax: Operands: Operation: Status Affected: Encoding: Description: Inclusive OR W with f [ label ] IORWF f,d 0 f 127 d [0,1] (W) .OR. (f) (W) Z
00 0100 dfff ffff Inclusive OR the W register to register 'f'. If 'd' is 0 the result is placed in the W register. If 'd' is 1 the result is placed back in register 'f'.
MOVF Syntax: Operands: Operation: Status Affected: Encoding: Description:
Move f [ label ] MOVF f,d 0 f 127 d [0,1] (f) (dest) Z
00 1000 dfff ffff The contents of register f is moved to destination d. If d = 0, destination is W register. If d = 1, the destination is file register f itself. d = 1 is useful to test a file register since status flag Z is affected.
Words: Cycles: Example
1 1
IORWF RESULT, 0 RESULT = W = 0x13 0x91 0x13 0x93
Words: Cycles: Example
1 1
MOVF FSR, 0 W =value in FSR register
Before Instruction
After Instruction
RESULT = W =
After Instruction
MOVLW Syntax: Operands: Operation: Status Affected: Encoding: Description:
Move literal to W [ label ] k (W) None
11 00XX kkkk kkkk The eight bit literal 'k' is loaded into W register. The don't cares will assemble as 0's.
MOVWF Syntax: Operands: Operation: Status Affected: Encoding: Description: Words: Cycles: Example
Move W to f [ label ] (W) (f) None
00 0000 1fff ffff Move data from W register to register 'f'.
MOVLW k
MOVWF
f
0 k 255
0 f 127
1 1
MOVWF OPTION OPTION = W = 0xFF 0x4F 0x4F 0x4F
Words: Cycles: Example
1 1
MOVLW W 0x5A = 0x5A
Before Instruction
After Instruction
After Instruction
OPTION = W =
DS30081F-page 60
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PIC16C8X
NOP Syntax: Operands: Operation: Status Affected: Encoding: Description: Words: Cycles: Example 1 1
NOP
No Operation [ label ] None No operation None
00 0000 0xx0 0000
RETFIE Syntax: Operands: Operation: Status Affected: Encoding: Description:
Return from Interrupt [ label ] None TOS (PC), 1 GIE None
00 0000 0000 1001 The Stack is popped and Top of Stack (TOS) is loaded into the PC. Interrupts are enabled by setting the Global Interrupt Enable bit. This is a two cycle instruction.
NOP
RETFIE
No operation.
Words: Cycles: Example
1 2
RETFIE
After Interrupt
PC = GIE = TOS 1
OPTION Syntax: Operands: Operation: Encoding: Description:
Load Option Register [ label ] None (W) OPTION
00 0000 0110 0010
RETLW Syntax: Operands: Operation: Status Affected: Encoding: Description:
Return Literal to W [ label ] RETLW k 0 k 255 k (W), TOS (PC) None
11 01xx kkkk kkkk The W register is loaded with the eight bit literal 'k'. The program counter is loaded from the top of the stack (the return address). This is a two cycle instruction.
OPTION
Status Affected: None
The contents of the W register are loaded in the OPTION register. This instruction is supported for code compatibility with PIC16C5X products. Since OPTION is a readable/writable register, the user can directly address it.
Words: Cycles: Example Note:
1 1 To maintain upward compatibility with future PIC16CXX products, do not use this instruction.
Words: Cycles: Example
1 2
CALL TABLE * * * TABLE ADDWF RETLW RETLW * * * RETLW ;W contains table ;offset value ;W now has table value ;W = offset ;Begin table ;
PC k1 k2
kn
; End of table
Before Instruction
W W = = 0x07 value of k7
After Instruction
(c) 1995 Microchip Technology Inc.
DS30081F-page 61
PIC16C8X
RETURN Syntax: Operands: Operation: Status Affected: Encoding: Description: Return from Subroutine [ label ] None TOS (PC) None
00 0000 0000 1000 Return from subroutine. The stack is popped and the Top of Stack (TOS) is loaded into the program counter. This is a two cycle instruction.
RRF Syntax: Operands: Operation: Status Affected: Encoding: Description:
Rotate Right f through Carry [ label ] RRF f,d 0 f 127 d [0,1] See description below C
00 1100 dfff ffff
RETURN
Words: Cycles: Example
1 2
RETURN
The contents of register 'f' are rotated one bit to the right through the Carry Flag. If 'd' is 0 the result is placed in the W register. If 'd' is 1 the result is placed
back in register 'f'. C Register f
After Interrupt
PC = TOS
Words: Cycles: Example
1 1
RRF REG1 C REG1,0 = = = = = 1110 0110 0 1110 0110 0111 0011 1
Before Instruction
After Instruction
REG1 W C
RLF Syntax: Operands: Operation: Status Affected: Encoding: Description:
Rotate Left f through Carry [ label ] 0 f 127 d [0,1] See description below C
00 1101 dfff ffff
SLEEP Syntax: Operands: Operation:
Go into Standby Mode [ label ] None 00h WDT, 0 WDT prescaler 1 TO, 0 PD TO, PD
00 0000 0110 0011
RLF
f,d
SLEEP
The contents of register 'f' are rotated one bit to the left through the Carry Flag. If 'd' is 0 the result is placed in the W register. If 'd' is 1 the result is stored back in register 'f'.
C Register f
Status Affected: Encoding: Description:
Words: Cycles: Example
1 1
RLF REG1,0 REG1 C = = = = = 1110 0110 0 1110 0110 1100 1100 1
The power down status bit (PD) is cleared. Time-out status bit (TO) is set. Watchdog Timer and its prescaler are cleared. The processor is put into SLEEP mode with the oscillator stopped. 1 1 SLEEP
Words: Cycles: Example:
Before Instruction
After Instruction
REG1 W C
DS30081F-page 62
(c) 1995 Microchip Technology Inc.
PIC16C8X
SUBLW Syntax: Operands: Operation: Status Affected: Encoding: Description: Subtract W from Literal [ label ] SUBLW k 0 k 255 k - (W) (W) C, DC, Z 11 110x kkkk kkkk The W register is subtracted (2's complement method) from the eight bit literal 'k'. The result is placed in the W register. 1 1 SUBLW
W C
SUBWF Syntax: Operands: Operation: Status Affected: Encoding: Description:
Subtract W from f [ label ] SUBWF f,d 0 f 127 d [0,1] (f) - (W) (dest) C, DC, Z 00 0010 dfff ffff Subtract (2's complement methodize W register from register 'f'. If 'd' is 0 the result is stored in the W register. If 'd' is 1 the result is stored back in register 'f'. 1 1 SUBWF REG1,1 Before Instruction
REG1 = 3 W =2 C =?
Words: Cycles: Example 1:
0x02
=1 =?
Words: Cycles: Example 1:
Before Instruction
After Instruction
W C =1 = 1; result is positive
Example 2:
Before Instruction
W C =2 =?
After Instruction
REG1 = 1 W =2 C = 1; result is positive
After Instruction
W C =0 = 1; result is zero
Example 2:
Before Instruction
REG1 = 2 W =2 C =?
Example 3:
Before Instruction
W C =3 =?
After Instruction
REG1 = 0 W =2 C = 1; result is zero
After Instruction
W C = FF = 0; result is negative
Example 3:
Before Instruction
REG1 = 1 W =2 C =?
After Instruction
REG1 = FF W =2 C = 0; result is negative
(c) 1995 Microchip Technology Inc.
DS30081F-page 63
PIC16C8X
SWAPF Syntax: Operands: Operation: Status Affected: Encoding: Description: Swap f [ label ] SWAPF f,d XORLW Syntax: Operands: Operation: Status Affected: Encoding: Description: 1110 dfff ffff Exclusive OR Literal with W [ label ] XORLW k 0 k 255 (W) .XOR. k (W) Z 11 1010 kkkk kkkk The contents of the W register are XOR'ed with the eight bit literal 'k'. The result is placed in the W register. 1 1 XORLW 0xAF
W SWAP F REG, 0 = 0xB5
0 f 127 d [0,1] (f<3:0>) (dest<7:4>), (f<7:4>) (dest<3:0>) None 00 The upper and lower nibbles of register 'f' are exchanged. If 'd' is 0 the result is placed in W register. If 'd' is 1 the result is placed in register 'f'. 1 1 Before Instruction
REG1 = 0xA5
Words: Cycles: Example:
Words: Cycles: Example
Before Instruction After Instruction
W = 0x1A
After Instruction
REG1 W = = 0xA5 0x5A
TRIS Syntax: Operands: Operation: Encoding: Description:
Load TRIS Register [ label ] TRIS 5f7 (W) TRIS register (f) f
XORWF Syntax: Operands: Operation:
Exclusive OR W with f [ label ] XORWF 0 f 127 d [0,1] (W) .XOR. (f) (dest) Z
00 0110 dfff ffff
f,d
Status Affected: None 00 0000 0110 0fff
The instruction is supported for code compatibility with the PIC16C5X products. Since TRIS registers are readable and writable, the user can directly address them.
Status Affected: Encoding: Description:
Words: Cycles: Example Note:
1 1 To maintain upward compatibility with future PIC16CXX products, do not use this instruction. Words: Cycles: Example
Exclusive OR the contents of the W register with register 'f'. If 'd' is 0 the result is stored in the W register. If 'd' is 1 the result is stored back in register 'f'. 1 1 XORWF
REG 1
Before Instruction
REG W = = 0xAF 0xB5
After Instruction
REG W = = 0x1A 0xB5
DS30081F-page 64
(c) 1995 Microchip Technology Inc.
PIC16C8X
10.0
10.1
DEVELOPMENT SUPPORT
Development Tools
The PIC16/17 microcontrollers are supported with a full range of hardware and software development tools: * * * * * * * * * PICMASTERTM Real-Time In-Circuit Emulator PRO MATETM Universal Programmer PICSTARTTM Low-Cost Prototype Programmer PICDEM-1 Low-Cost Demonstration Board PICDEM-2 Low-Cost Demonstration Board MPASM Assembler MPSIM Software Simulator C Compiler (MP-C) Fuzzy logic development system (fuzzyTECH(R)-MP)
The PICMASTER Emulator System has been designed as a real-time emulation system with advanced features that are generally found on more expensive development tools. The PC compatible 386 (and better) machine platform and Microsoft(R) Windows(R) 3.x environment was chosen to best make these features available to you, the end user. The PICMASTER Universal Emulator System consists primarily of four major components: * * * * Host-Interface Card Emulator Control Pod Target-Specific Emulator Probe PC-Host Emulation Control Software
The Windows operating system allows the developer to take full advantage of the many powerful features and functions of the PICMASTER system. PICMASTER emulation can operate in one window, while a text editor is running in a second window. PC-Host Emulation Control software takes full advantage of Dynamic Data Exchange (DDE), a feature of Windows. DDE allows data to be dynamically transferred between two or more Windows programs. With this feature, data collected with PICMASTER can be automatically transferred to a spreadsheet or database program for further analysis. Under Windows, as many as four PICMASTER emulators can be run simultaneously from the same PC making development of multi-microcontroller systems possible (e.g., a system containing a PIC16CXX processor and a PIC17CXX processor). The PICMASTER probes specifications are shown in Table 10-1.
10.2
PICMASTER: High Performance Universal In-Circuit Emulator with MPLAB IDE
The PICMASTER Universal In-Circuit Emulator (Figure 10-1) is intended to provide the product development engineer with a complete microcontroller design tool set for all microcontrollers in the PIC16C5X, PIC16CXX and PIC17CXX families. PICMASTER is supplied with the MPLABTM Integrated Development Environment (IDE), which allows editing, "make" and download, and source debugging from a single environment. Interchangeable target probes allow the system to be easily reconfigured for emulation of different processors. The universal architecture of the PICMASTER allows expansion to support all new PIC16C5X, PIC16CXX and PIC17CXX microcontrollers.
FIGURE 10-1: PICMASTER SYSTEM CONFIGURATION
5 VDC In-Line Power Supply (Optional) Power Switch Power Connector 90 - 250 VAC
Windows 3.x
PC Bus
Interchangeable Emulator Probe
PC-Interface
Common Interface Card PC Compatible Computer
PICMASTER Emulator Pod
Logic Probes
(c) 1995 Microchip Technology Inc.
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TABLE 10-1: PICMASTER PROBE SPECIFICATION
PROBE Devices PICMASTER PROBE PROBE-16D PROBE-16D PROBE-16D PROBE-16D(1) PROBE-16D(1) PROBE-16D PROBE-16D(1) PROBE-16D PROBE-16D(1) PROBE-16D PROBE-16D PROBE-16D(1) PROBE-16D PROBE-16D PROBE-16D
(1)
TABLE 10-1:
PICMASTER PROBE SPECIFICATION
PROBE PICMASTER PROBE PROBE-16F PROBE-16F(1) PROBE-16H PROBE-16H PROBE-16H PROBE-16B(1) PROBE-16B PROBE-16B
(1)
Maximum Frequency 20 MHz 20 MHz 20 MHz 20 MHz 20 MHz 20 MHz 20 MHz 20 MHz 20 MHz 20 MHz 20 MHz 20 MHz 20 MHz 20 MHz 20 MHz 10 MHz 10 MHz 10 MHz 10 MHz 10 MHz 10 MHz 10 MHz 10 MHz
Operating Voltage 4.5V - 5.5V 4.5V - 5.5V 4.5V - 5.5V 4.5V - 5.5V 4.5V - 5.5V 4.5V - 5.5V 4.5V - 5.5V 4.5V - 5.5V 4.5V - 5.5V 4.5V - 5.5V 4.5V - 5.5V 4.5V - 5.5V 4.5V - 5.5V 4.5V - 5.5V 4.5V - 5.5V 4.5V - 5.5V 4.5V - 5.5V 4.5V - 5.5V 4.5V - 5.5V 4.5V - 5.5V 4.5V - 5.5V 4.5V - 5.5V 4.5V - 5.5V
Devices
Maximum Frequency 10 MHz 10 MHz 10 MHz 10 MHz 10 MHz 10 MHz 10 MHz 10 MHz 10 MHz 10 MHz 10 MHz 10 MHz 10 MHz 10 MHz 10 MHz 20 MHz 20 MHz 20 MHz
Operating Voltage 4.5V - 5.5V 4.5V - 5.5V 4.5V - 5.5V 4.5V - 5.5V 4.5V - 5.5V 4.5V - 5.5V 4.5V - 5.5V 4.5V - 5.5V 4.5V - 5.5V 4.5V - 5.5V 4.5V - 5.5V 4.5V - 5.5V 4.5V - 5.5V 4.5V - 5.5V 4.5V - 5.5V 4.5V - 5.5V 4.5V - 5.5V 4.5V - 5.5V
PIC16C54 PIC16C54A PIC16CR54 PIC16CR54A PIC16CR54B PIC16C55 PIC16CR55 PIC16C56 PIC16CR56 PIC16C57 PIC16CR57A PIC16CR57B PIC16C58A PIC16CR58A PIC16CR58B PIC16C61 PIC16C62 PIC16C62A PIC16CR62 PIC16C63 PIC16C64 PIC16C64A PIC16CR64
PIC16C65 PIC16C65A PIC16C620 PIC16C621 PIC16C622 PIC16C70 PIC16C71 PIC16C71A PIC16C72 PIC16C73 PIC16C73A PIC16C74 PIC16C74A PIC16C83 PIC16C84 PIC17C42 PIC17C43 PIC17C44
PROBE-16F(1) PROBE-16F PROBE-16F(1) PROBE-16F PROBE-16F
(1)
PROBE-16C PROBE-16C PROBE-17B PROBE-17B PROBE-17B
PROBE-16G PROBE-16E PROBE-16E(1) PROBE-16E
(1)
PROBE-16F(1) PROBE-16E PROBE-16E
(1) (1)
Note 1: This PICMASTER probe can be used to functionally emulate the device listed in the previous column. Contact your Microchip sales office for details.
PROBE-16E
DS30081F-page 66
(c) 1995 Microchip Technology Inc.
PIC16C8X
10.3 PRO MATE: Universal Programmer 10.5
The PRO MATE Universal Programmer is a full-featured programmer capable of operating in stand-alone mode as well as PC-hosted mode. The PRO MATE has programmable VDD and VPP supplies which allows it to verify programmed memory at VDD min and VDD max for maximum reliability. It has an LCD display for displaying error messages, keys to enter commands and a modular detachable socket assembly to support various package types. In stand- alone mode the PRO MATE can read, verify or program PIC16C5X, PIC16CXX and PIC17CXX devices. It can also set configuration and code-protect bits in this mode. In PC-hosted mode, the PRO MATE connects to the PC via one of the COM (RS-232) ports. PC based user-interface software makes using the programmer simple and efficient. The user interface is full-screen and menu-based. Full screen display and editing of data, easy selection of bit configuration and part type, easy selection of VDD min, VDD max and VPP levels, load and store to and from disk files (Intel(R) hex format) are some of the features of the software. Essential commands such as read, verify, program and blank check can be issued from the screen. Additionally, serial programming support is possible where each part is programmed with a different serial number, sequential or random. The PRO MATE has a modular "programming socket module". Different socket modules are required for different processor types and/or package types. PRO MATE supports all PIC16C5X, PIC16CXX and PIC17CXX processors.
PICDEM-1 Low-Cost PIC16/17 Demonstration Board
The PICDEM-1 is a simple board which demonstrates the capabilities of several of Microchip's microcontrollers. The microcontrollers supported are: PIC16C5X (PIC16C54 to PIC16C58A), PIC16C61, PIC16C62X, PIC16C71, PIC16C8X, PIC17C42, PIC17C43 and PIC17C44. All necessary hardware and software is included to run basic demo programs. The users can program the sample microcontrollers provided with the PICDEM-1 board, on a PRO MATE or PICSTART-16B programmer, and easily test firmware. The user can also connect the PICDEM-1 board to the PICMASTER emulator and download the firmware to the emulator for testing. Additional prototype area is available for the user to build some additional hardware and connect it to the microcontroller socket(s). Some of the features include an RS-232 interface, a potentiometer for simulated analog input, push-button switches and eight LEDs connected to PORTB.
10.6
PICDEM-2 Low-Cost PIC16CXX Demonstration Board
10.4
PICSTART Low-Cost Development System
The PICSTART programmer is an easy to use, very low-cost prototype programmer. It connects to the PC via one of the COM (RS-232) ports. A PC-based user interface software makes using the programmer simple and efficient. The user interface is full-screen and menu-based. PICSTART is not recommended for production programming.
The PICDEM-2 is a simple demonstration board that supports the PIC16C64, PIC16C65, PIC16C73 and PIC16C74 microcontrollers. All the necessary hardware and software is included to run the basic demonstration programs. The user can program the sample microcontrollers provided with the PICDEM-2 board, on a PRO MATE programmer or PICSTART-16C, and easily test firmware. The PICMASTER emulator may also be used with the PICDEM-2 board to test firmware. Additional prototype area has been provided to the user for adding additional hardware and connecting it to the microcontroller socket(s). Some of the features include a RS-232 interface, push-button switches, a potentiometer for simulated analog input, a Serial EEPROM to demonstrate usage of the I2C bus and separate headers for connection to an LCD module and a keypad.
(c) 1995 Microchip Technology Inc.
DS30081F-page 67
PIC16C8X
10.7 MPLAB Integrated Development Environment Software 10.8 Assembler (MPASM)
The MPASM Cross Assembler is a PC-hosted symbolic assembler. It supports all microcontroller series including the PIC16C5X, PIC16CXX, and PIC17CXX families. MPASM offers full featured Macro capabilities, conditional assembly, and several source and listing formats. It generates various object code formats to support Microchip's development tools as well as third party programmers. MPASM allows full symbolic debugging from the Microchip Universal Emulator System (PICMASTER). MPASM has the following features to assist in developing software for specific use applications. * Provides translation of Assembler source code to object code for all Microchip microcontrollers. * Macro assembly capability * Produces all the files (Object, Listing, Symbol, and special) required for symbolic debug with Microchip's emulator systems. * Supports Hex (default), Decimal and Octal source and listing formats. MPASM provides a rich directive language to support programming of the PIC16/17. Directives are helpful in making the development of your assemble source code shorter and more maintainable. * Data Directives are those that control the allocation of memory and provide a way to refer to data items symbolically (i.e., by meaningful names). * Control Directives control the MPASM listing display. They allow the specification of titles and sub-titles, page ejects and other listing control. This eases the readability of the printed output file. * Conditional Directives permit sections of conditionally assembled code. This is most useful where additional functionality may wished to be added depending on the product (less functionality for the low end product, then for the high end product). Also this is very helpful in the debugging of a program. * Macro Directives control the execution and data allocation within macro body definitions. This makes very simple the re-use of functions in a program as well as between programs.
The MPLAB Software brings an ease of software development previously unseen in the 8-bit microcontroller market. MPLAB is a windows based application which contains: * A full featured editor * Three operating modes - editor - emulator - simulator (available soon) * A project manager * Customizable tool bar and key mapping * A status bar with project information * Extensive on-line help MPLAB allows you to: * edit your source files (either assembly or "C") * one touch assemble (or compile) and download to PIC16/17 tools (automatically updates all project information) * debug using: - source files - absolute listing file * transfer data dynamically via DDE (soon to be replaced by OLE) * run up to four emulators on the same PC The ability to use MPLAB with Microchip's simulator (available soon) allows a consistent platform and the ability to easily switch from the low cost simulator to the full featured emulator with minimal retraining due to development tools.
DS30081F-page 68
(c) 1995 Microchip Technology Inc.
PIC16C8X
10.9 Software Simulator (MPSIM) 10.11
The MPSIM Software Simulator allows code development in a PC host environment. It allows the user to simulate the PIC16/17 series microcontrollers on an instruction level. On any given instruction, the user may examine or modify any of the data areas or provide external stimulus to any of the pins. The input/output radix can be set by the user and the execution can be performed in; single step, execute until break, or in a trace mode. MPSIM fully supports symbolic debugging using MP-C and MPASM. The Software Simulator offers the low cost flexibility to develop and debug code outside of the laboratory environment making it an excellent multi-project software development tool.
Fuzzy Logic Development System (fuzzyTECH-MP)
fuzzyTECH-MP fuzzy logic development tool is available in two versions - a low cost introductory version, MP Explorer, for designers to gain a comprehensive working knowledge of fuzzy logic system design; and a full-featured version, fuzzyTECH-MP, edition for implementing more complex systems.
Both versions include Microchip's fuzzyLABTM demonstration board for hands-on experience with fuzzy logic systems implementation.
10.12
Development Systems
10.10
C Compiler (MP-C)
For convenience, the development tools are packaged into comprehensive systems as listed in Table 10-2.
The MP-C Code Development System is a complete 'C' compiler and integrated development environment for Microchip's PIC16/17 family of microcontrollers. The compiler provides powerful integration capabilities and ease of use not found with other compilers. For easier source level debugging, the compiler provides symbol information that is compatible with the PICMASTER Universal Emulator memory display (PICMASTER emulator software versions 1.13 and later). The MP-C Code Development System is supplied directly by Byte Craft Limited of Waterloo, Ontario, Canada. If you have any questions, please contact your regional Microchip FAE or Microchip technical support personnel at (602) 786-7627.
TABLE 10-2:
Item 1. 2. 3.
DEVELOPMENT SYSTEM PACKAGES
Name System Description PICMASTER In-Circuit Emulator, PRO MATE Programmer, Assembler, Software Simulator, Samples and your choice of Target Probe. PICSTART Low-Cost Prototype Programmer, Assembler, Software Simulator and Samples. PRO MATE Universal Programmer, full featured stand-alone or PC-hosted programmer, Assembler, Simulator
PICMASTER System PICSTART System PRO MATE System
(c) 1995 Microchip Technology Inc.
DS30081F-page 69
PIC16C8X
NOTES:
DS30081F-page 70
(c) 1995 Microchip Technology Inc.
PIC16C8X
Applicable Devices 83 R83 84 84A R84
11.0
ELECTRICAL CHARACTERISTICS FOR PIC16C84
Absolute Maximum Ratings Ambient temperature under bias.............................................................................................................-55C to +125C Storage temperature .............................................................................................................................. -65C to +150C Voltage on VDD with respect to VSS ............................................................................................................... 0 to +7.5V Voltage on MCLR with respect to VSS (Note 2).................................................................................................0 to +14V Voltage on all other pins with respect to VSS .................................................................................. -0.6V to (VDD + 0.6V) Total power dissipation (Note 1)...........................................................................................................................800 mW Maximum current out of VSS pin ...........................................................................................................................150 mA Maximum current into VDD pin ..............................................................................................................................100 mA Input clamp current, IIK (VI < 0 or VI > VDD) ..................................................................................................................... 20 mA Output clamp current, IOK (V0 < 0 or V0 >VDD) ............................................................................................................... 20 mA Maximum output current sunk by any I/O pin..........................................................................................................25 mA Maximum output current sourced by any I/O pin ....................................................................................................20 mA Maximum current sunk by PORTA ..........................................................................................................................80 mA Maximum current sourced by PORTA .....................................................................................................................50 mA Maximum current sunk by PORTB........................................................................................................................150 mA Maximum current sourced by PORTB...................................................................................................................100 mA Note 1: Power dissipation is calculated as follows: Pdis = VDD x {IDD - IOH} + {(VDD-VOH) x IOH} + (VOl x IOL) Note 2: Voltage spikes below VSS at the MCLR pin, inducing currents greater than 80 mA, may cause latch-up. Thus, a series resistor of 50-100 should be used when applying a "low" level to the MCLR pin rather than pulling this pin directly to VSS. NOTICE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.
TABLE 11-1:
OSC RC VDD: IDD: IPD: Freq: VDD: IDD: IPD: Freq: VDD: IDD: IPD: Freq:
CROSS REFERENCE OF DEVICE SPECS FOR OSCILLATOR CONFIGURATIONS AND FREQUENCIES OF OPERATION (COMMERCIAL DEVICES)
PIC16C84-04 4.0V to 6.0V 4.5 mA max. at 5.5V 100 A max. at 4.0V WDT dis 4.0 MHz max. 4.0V to 6.0V 4.5 mA max. at 5.5V 100 A max. at 4.0V WDT dis 4.0 MHz max. 4.5V to 5.5V 4.5 mA typ. at 5.5V 40.0 A typ. at 4.5V WDT dis 4.0 MHz max. PIC16C84-10 VDD: 4.5V to 5.5V IDD: 1.8 mA typ. at 5.5V IPD: 40.0 A typ. at 4.5V WDT dis Freq: 4.0 MHz max. VDD: 4.5V to 5.5V IDD: 1.8 mA typ. at 5.5V IPD: 40.0 A typ. at 4.5V WDT dis Freq: 4.0 MHz max. VDD: 4.5V to 5.5V IDD: 10 mA max. at 5.5V typ. IPD: 40.0 A typ. at 4.5V WDT dis Freq: 10 MHz max. Do not use in LP mode PIC16LC84-04 VDD: 2.0V to 6.0V IDD: 4.5 mA typ. at 5.5V IPD: 100 A typ. at 4V WDT dis Freq: 2.0 MHz max. VDD: 2.0V to 6.0V IDD: 4.5 mA typ. at 5.5V IPD: 100 A typ. at 4V WDT dis Freq: 2.0 MHz max. Do not use in HS mode
XT
HS
VDD: 2.0V to 6.0V VDD: 4.0V to 6.0V IDD: 60 A typ. at 32 kHz, 2.0V IDD: 400 A max. at 32 kHz, 2.0V IPD: 26 A typ. at 2.0V WDT dis IPD: 100 A max. at 4.0V WDT dis Freq: 200 kHz max. Freq: 200 kHz max. The shaded sections indicate oscillator selections which are tested for functionality, but not for MIN/MAX specifications. It is recommended that the user select the device type that ensures the specifications required.
LP
(c) 1995 Microchip Technology Inc.
DS30081F-page 71
Thi d
t
t d ith F
Mk
404
PIC16C8X
Applicable Devices 83 R83 84 84A R84 11.1 DC CHARACTERISTICS: PIC16C84-04 (Commercial, Industrial) PIC16C84-10 (Commercial, Industrial)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial and 0C TA +70C for commercial Min Typ Max Units Conditions 4.0 4.5 1.5* -- -- -- -- VSS 6.0 5.5 -- -- V V V V XT, RC and LP osc configuration HS osc configuration Device in SLEEP mode See section on Power-on Reset for details
DC CHARACTERISTICS
Parameter No.
Sym VDD VDR
Characteristic Supply Voltage
D001 D001A D002 D003
D004
D010 D010A D013
RAM Data Retention Voltage (Note 1) VPOR VDD start voltage to ensure Power-on Reset SVDD VDD rise rate to ensure Power-on Reset IDD Supply Current (Note 2)
0.05*
--
--
V/ms See section on Power-on Reset for details
-- -- --
1.8 7.3 5.0
4.5 10 10
mA mA mA
D020 IPD Power-down Current -- 40 100 A D021 (Note 3) -- 38 100 A D021A -- 38 100 A * These parameters are characterized but not tested. Data in "Typ" column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail to rail; all I/O pins tristated, pulled to VDD, T0CKI = VDD, MCLR = VDD; WDT enabled/disabled as specified. 3: The power down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD or VSS. 4: For RC osc configuration, current through Rext is not included. The current through the resistor can be estimated by the formula IR = VDD/2Rext (mA) with Rext in kOhm.
RC and XT osc configuration (Note 4) FOSC = 4 MHz, VDD = 5.5V FOSC = 4 MHz, VDD = 5.5V (During EEPROM programming) HS osc configuration (PIC16C84-10) FOSC = 10 MHz, VDD = 5.5V VDD = 4.0V, WDT enabled, -40C to +85C VDD = 4.0V, WDT disabled, -0C to +70C VDD = 4.0V, WDT disabled, -40C to +85C
DS30081F-page 72
(c) 1995 Microchip Technology Inc.
PIC16C8X
Applicable Devices 83 R83 84 84A R84 11.2 DC CHARACTERISTICS: PIC16LC84-04 (Commercial, Industrial)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial and 0C TA +70C for commercial Min Typ Max Units Conditions 2.0 1.5 * -- -- -- VSS 6.0 -- -- V V V XT, RC, and LP osc configuration Device in SLEEP mode See section on Power-on Reset for details
DC CHARACTERISTICS
Parameter No.
Sym VDD VDR
Characteristic
D001 D002 D003
D004
D010 D010A
Supply Voltage RAM Data Retention Voltage (Note 1) VPOR VDD start voltage to ensure Power-on Reset SVDD VDD rise rate to ensure Power-on Reset Supply Current IDD (Note 2)
0.05*
--
--
V/ms See section on Power-on Reset for details
-- --
1.8 7.3
4.5 10
mA mA A
D014
--
60
400
IPD D020 Power-down Current -- 26 100 A D021 (Note 3) -- 26 100 A D021A -- 26 100 A * These parameters are characterized but not tested. Data in "Typ" column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1=external square wave, from rail to rail; all I/O pins tristated, pulled to VDD, T0CKI = VDD, MCLR = VDD; WDT enabled/disabled as specified. 3: The power down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD or VSS. 4: For RC osc configuration, current through Rext is not included. The current through the resistor can be estimated by the formula IR = VDD/2Rext (mA) with Rext in kOhm.
RC and XT osc configuration (Note 4) FOSC = 2 MHz, VDD = 5.5V FOSC = 2 MHz, VDD = 5.5V (During EEPROM programming) LP osc configuration FOSC = 32 kHz, VDD = 2.0V WDT disabled VDD = 2.0V, WDT enabled, -40C to +85C VDD = 2.0V, WDT disabled, 0C to +70C VDD = 2.0V, WDT disabled, -40C to +85C
(c) 1995 Microchip Technology Inc.
DS30081F-page 73
PIC16C8X
Applicable Devices 83 R83 84 84A R84 11.3 DC CHARACTERISTICS: PIC16C84-04 (Commercial, Industrial) PIC16C84-10 (Commercial, Industrial) PIC16LC84-04 (Commercial, Industrial)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial and 0C TA +70C for commercial Operating voltage VDD range as described in DC spec Section 11-1 and Section 11-3. Characteristic Input Low Voltage I/O ports with TTL buffer Min Typ Max Units Conditions
DC CHARACTERISTICS
Parameter Sym No.
VIL D030 D030A D031 D032 D033
D040 D040A D041 D042 D043 D050 D070
D060 D061 D063
with Schmitt Trigger buffer MCLR, RA4/T0CKI, OSC1 (RC mode) OSC1 (XT, HS and LP modes) Vss Input High Voltage VIH I/O ports with TTL buffer 0.36VDD 0.48VDD with Schmitt Trigger buffer 0.45VDD MCLR, RA4/T0CKI, OSC1 0.85VDD (RC mode) OSC1 (XT, HS and LP modes) 0.7VDD VHYS Hysteresis of TBD Schmitt Trigger inputs 50* IPURB PORTB weak pull-up current Input Leakage Current (Notes 2, 3) IIL I/O ports -- MCLR, RA4/T0CKI OSC1/CLKIN -- --
VSS VSS VSS Vss
-- 0.8 -- 0.16VDD -- 0.2VDD -- 0.2VDD -- 0.3VDD
V V V V V
4.5 VDD 5.5V entire range (Note 4) entire range
Note1
-- -- -- --
--
VDD VDD VDD VDD
--
V
4.5 VDD 5.5V entire range (Note 4) entire range
V V V Note1
250*
400*
A VDD = 5V, VPIN = VSS
-- -- --
1 5 5
A Vss VPIN VDD, Pin at hi-impedance A Vss VPIN VDD A Vss VPIN VDD, XT, HS and LP osc configuration
Output Low Voltage I/O ports -- -- 0.6 V IOL = 8.5 mA, VDD = 4.5V OSC2/CLKOUT -- -- 0.6 V IOL = 1.6 mA, VDD = 4.5V (RC osc configuration) Output High Voltage D090 VOH I/O ports (Note 3) VDD - 0.7 -- -- V IOH = -3.0 mA, VDD = 4.5V D093 OSC2/CLKOUT VDD - 0.7 -- -- V IOH = -1.3 mA, VDD = 4.5V (RC osc configuration) * These parameters are characterized but not tested. Data in "Typ" column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PIC16C84 be driven with external clock in RC mode. 2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 3: Negative current is defined as coming out of the pin. 4: The user may use better of the two specs. D080 D083 VOL
DS30081F-page 74
(c) 1995 Microchip Technology Inc.
PIC16C8X
Applicable Devices 83 R83 84 84A R84 11.4 DC CHARACTERISTICS: PIC16C84-04 (Commercial, Industrial) PIC16C84-10 (Commercial, Industrial) PIC16LC84-04 (Commercial, Industrial)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial and 0C TA +70C for commercial Operating voltage VDD range as described in DC spec Section 11-1 and Section 11-3. Min Typ Max Units Conditions
DC CHARACTERISTICS
Parameter No.
Sym
Characteristic
D100
Capacitive Loading Specs on Output Pins COSC2 OSC2/CLKOUT pin
--
--
15
pF
In XT, HS and LP modes when external clock is used to drive OSC1.
D101
CIO
All I/O pins and OSC2 (RC mode) Data EEPROM Memory Endurance VDD for read/write Erase/Write cycle time Program EEPROM Memory Endurance VDD for read
--
--
50
pF
D120 D121 D122 D130 D131
ED VDRW TDEW EP VPR
100,000 1,000,000 VMIN -- -- 100 VMIN 10 -- --
-- 6.0 -- -- 6.0
E/W V VMIN = Minimum operating voltage ms Note1
E/W V VMIN = Minimum operating voltage D132 VPEW VDD for erase/write 4.5 -- 5.5 V D133 TPEW Erase/Write cycle time -- 10 -- ms Note1 Data in "Typ" column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: The user should use interrupts or poll the EEIF or WR bits to ensure the write cycle has completed.
(c) 1995 Microchip Technology Inc.
DS30081F-page 75
PIC16C8X
Applicable Devices 83 R83 84 84A R84 TABLE 11-2: TIMING PARAMETER SYMBOLOGY
The timing parameter symbols have been created following one of the following formats: 1. TppS2ppS 2. TppS T F Frequency Lowercase symbols (pp) and their meanings: pp ck CLKOUT io I/O port mc MCLR Uppercase symbols and their meanings: S F Fall H High I Invalid (Hi-impedance) L Low
T
Time
osc t0
OSC1 T0CKI
P R V Z
Period Rise Valid Hi-impedance
FIGURE 11-1: PARAMETER MEASUREMENT INFORMATION
0.7 VDD XTAL 0.8 VDD RC (High) 0.3 VDD XTAL 0.15 VDD RC (Low) OSC1 Measurement Points I/O Port Measurement Points 2.0 VDD (High) 0.2 VDD (Low)
All timings are measured between high and low measurement points as indicated in the figure.
FIGURE 11-2: LOAD CONDITIONS
Load Condition 1 VDD/2 RL Pin VSS RL = CL = 464 50 pF 15 pF for all pins except OSC2. for OSC2 output. CL Pin VSS CL Load Condition 2
DS30081F-page 76
(c) 1995 Microchip Technology Inc.
PIC16C8X
Applicable Devices 83 R83 84 84A R84 11.5 Timing Diagrams and Specifications
FIGURE 11-3: EXTERNAL CLOCK TIMING
Q4 OSC1 1 2 CLKOUT 3 3 4 4 Q1 Q2 Q3 Q4 Q1
TABLE 11-3:
Parameter No.
EXTERNAL CLOCK TIMING REQUIREMENTS
Sym Fos Characteristic External CLKIN Frequency (Note 1) Min Typ Max Units Conditions
DC -- 2 MHz XT, RC osc PIC16LC84-04 DC -- 4 MHz XT, RC osc PIC16C84-04 DC -- 10 MHz HS osc PIC16C84-10 DC -- 200 kHz LP osc PIC16LC84-04 Oscillator Frequency DC -- 2 MHz RC osc PIC16LC84-04 (Note 1) DC -- 4 MHz RC osc PIC16C84-04 0.1 -- 2 MHz XT osc PIC16LC84-04 0.1 -- 4 MHz XT osc PIC16C84-04 1 -- 10 MHz HS osc PIC16C84-10 DC -- 200 kHz LP osc PIC16LC84-04 500 -- -- ns XT, RC osc PIC16LC84-04 1 TOSC External CLKIN Period (Note 1) 250 -- -- ns XT, RC osc PIC16C84-04 100 -- -- ns HS osc PIC16C84-10 5 -- -- s LP osc PIC16LC84-04 Oscillator Period 500 -- -- ns RC osc PIC16LC84-04 (Note 1) 250 -- -- ns RC osc PIC16C84-04 500 -- 10,000 ns XT osc PIC16LC84-04 250 -- 10,000 ns XT osc PIC16C84-04 100 -- 1,000 ns HS osc PIC16C84-10 5 -- -- s LP osc PIC16LC84-04 0.4 4/Fosc DC s 2 TCY Instruction Cycle Time (Note 1) 3 TosL, Clock in (OSC1) High or Low Time 60 * -- -- ns XT osc PIC16LC84-04 TosH 50 * -- -- ns XT osc PIC16C84-04 2* -- -- s LP osc PIC16LC84-04 35 * -- -- ns HS osc PIC16C84-10 4 TosR, Clock in (OSC1) Rise or Fall Time 25 * -- -- ns XT osc PIC16C84-04 TosF 50 * -- -- ns LP osc PIC16LC84-04 15 * -- -- ns HS osc PIC16C84-10 Data in "Typ" column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at "min." values with an external clock applied to the OSC1 pin. When an external clock input is used, the "Max." cycle time limit is "DC" (no clock) for all devices.
(c) 1995 Microchip Technology Inc.
DS30081F-page 77
PIC16C8X
Applicable Devices 83 R83 84 84A R84 FIGURE 11-4: CLKOUT AND I/O TIMING
Q4 OSC1 10 CLKOUT 13 14 I/O Pin (input) 17 I/O Pin (output) old value 20, 21 Note: All tests must be done with specified capacitive loads (Figure 11-2) 50 pF on I/O pins and CLKOUT. 15 new value 19 18 22 23 12 16 11 Q1 Q2 Q3
TABLE 11-4:
Parameter No. 10 10A 11 11A 12 12A 13 13A 14 15 16 17 18 19 20 20A 21 21A 22 22A 23 23A *
CLKOUT AND I/O TIMING REQUIREMENTS
Sym TosH2ckL Characteristic OSC1 to CLKOUT PIC16C84 PIC16LC84 TosH2ckH TckR TckF TckL2ioV TioV2ckH TckH2ioI TosH2ioV TosH2ioI TioV2osH TioR TioF Tinp Trbp OSC1 to CLKOUT CLKOUT rise time CLKOUT fall time PIC16C84 PIC16LC84 PIC16C84 PIC16LC84 PIC16C84 PIC16LC84 CLKOUT to Port out valid Port in valid before CLKOUT OSC1 (Q1 cycle) to Port out valid PIC16C84 PIC16LC84 PIC16C84 PIC16LC84 Min -- -- -- -- -- -- -- -- -- 0.30TCY + 30 * 0.30TCY + 80 * 0* -- -- TBD TBD -- -- -- -- 20 * 55 * 20 * 55 * Typ 15 15 15 15 15 15 15 15 -- -- -- -- -- -- -- -- 10 10 10 10 -- -- -- -- Max 30 * 120 * 30 * 120 * 30 * 100 * 30 * 100 * 0.5TCY +20 * -- -- -- 125 * 250 * -- -- 25 * 60 * 25 * 60 * -- -- -- -- Units Conditions ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Note 1 Note 1 Note 1 Note 1 Note 1 Note 1 Note 1 Note 1 Note 1 Note 1 Note 1 Note 1
Port in hold after CLKOUT
OSC1 (Q2 cycle) to Port input invalid (I/O in hold time) Port input valid to OSC1 (I/O in setup time) Port output rise time Port output fall time INT pin high or low time RB7:RB4 change INT high or low time PIC16C84 PIC16LC84 PIC16C84 PIC16LC84 PIC16C84 PIC16LC84 PIC16C84 PIC16LC84
These parameters are characterized but not tested. Data in "Typ" column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Measurements are taken in RC Mode where CLKOUT output is 4 x TOSC.
DS30081F-page 78
(c) 1995 Microchip Technology Inc.
PIC16C8X
Applicable Devices 83 R83 84 84A R84 FIGURE 11-5: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING
VDD MCLR Internal POR 33 PWRT Time-out OSC Time-out Internal RESET Watchdog Timer RESET 34 I/O Pins 32 30
31 34
TABLE 11-5:
Parameter No. 30 31 32 33 34 *
RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER REQUIREMENTS
Sym TmcL Twdt Tost Tpwrt TIOZ Characteristic MCLR Pulse Width (low) Watchdog Timer Time-out Period (No Prescaler) Oscillation Start-up Timer Period Power-up Timer Period I/O Hi-impedance from MCLR Low or reset Min 350 * 150 * 7* -- 28 * -- Typ -- -- 18 1024TOSC 72 -- Max -- -- 33 * -- 132 * 100 * Units ns ns ms ms ms ns Conditions 2.0V VDD 3.0V 3.0V VDD 6.0V VDD = 5V TOSC = OSC1 period VDD = 5.0V
These parameters are characterized but not tested. Data in "Typ" column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested.
(c) 1995 Microchip Technology Inc.
DS30081F-page 79
PIC16C8X
Applicable Devices 83 R83 84 84A R84 FIGURE 11-6: TIMER0 CLOCK TIMINGS
RA4/T0CKI
40
41
42
TABLE 11-6:
Parameter No. 40
TIMER0 CLOCK REQUIREMENTS
Min No Prescaler With Prescaler 0.5TCY + 20 * 50 * 30 * 0.5TCY + 20 * 50 * 20 * TCY + 40 * N Typ Max Units Conditions -- -- -- -- -- -- -- -- -- -- -- -- -- -- ns ns ns ns ns ns ns 2.0V VDD 3.0V 3.0V VDD 6.0V N = prescale value (2, 4, ..., 256) 2.0V VDD 3.0V 3.0V VDD 6.0V
Sym Characteristic Tt0H T0CKI High Pulse Width
41
Tt0L T0CKI Low Pulse Width
No Prescaler With Prescaler
42 *
Tt0P T0CKI Period
These parameters are characterized but not tested. Data in "Typ" column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested.
DS30081F-page 80
(c) 1995 Microchip Technology Inc.
PIC16C8X
Applicable Devices 83 R83 84 84A R84
12.0
DC & AC CHARACTERISTICS GRAPHS/TABLES FOR PIC16C84
The data graphs and tables provided in this section are for design guidance and are not tested or guaranteed. In some graphs or tables the data presented is outside specified operating range (e.g., outside specified VDD range). This is for information only and devices are guaranteed to operate properly only within the specified range. The data presented in this section is a statistical summary of data collected on units from different lots over a period of time. "Typical" represents the mean of the distribution while 'max' or 'Min' represents (mean + 3) and (mean - 3) respectively where is standard deviation.
FIGURE 12-1: TYPICAL RC OSCILLATOR FREQUENCY vs. TEMPERATURE
FOSC FOSC (25C) 1.10 1.08 1.06 1.04 1.02 1.00 VDD = 5.5V 0.98 0.96 0.94 VDD = 3.5V 0.92 0.90 0.88 0 10 20 25 30 T(C) 40 50 60 70 Rext 10 k Cext = 100 pF Frequency Normalized To +25C
TABLE 12-1:
Cext 20 pF
RC OSCILLATOR FREQUENCIES *
Rext 3.3k 5.1k 10k 100k 3.3k 5.1k 10k 100k 3.3k 5.1k 10k 100k 4.68 MHz 3.94 MHz 2.34 MHz 250.16 kHz 1.49 MHz 1.12 MHz 620.31 kHz 90.25 kHz 524.24 kHz 415.52 kHz 270.33 kHz 25.37 kHz Average Fosc @ 5V, 25C 27% 25% 29% 33% 25% 25% 30% 26% 28% 30% 26% 25%
100 pF
300 pF
*Measured in PDIP Packages.The percentage variation indicated here is part to part variation due to normal process distribution. The variation indicated is 3 standard deviation from average value.
(c) 1995 Microchip Technology Inc.
DS30081F-page 81
Thi d
t
t d ith F
Mk
404
PIC16C8X
Applicable Devices 83 R83 84 84A R84 FIGURE 12-2: TYPICAL RC OSCILLATOR FREQUENCY vs. VDD
5.5 5.0 R = 3.3k 4.5 4.0 R = 5k 3.5 FOSC (MHz) 3.0 Cext = 20 pF, T = 25C 2.5 2.0 R = 10k 1.5 1.0 R = 100k 0.5 0.0 2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VDD (Volts)
DS30081F-page 82
(c) 1995 Microchip Technology Inc.
PIC16C8X
Applicable Devices 83 R83 84 84A R84 FIGURE 12-3: TYPICAL RC OSCILLATOR FREQUENCY vs. VDD
2.2 2.0 1.8 R = 3.3k 1.6 1.4 FOSC (MHz) R = 5k 1.2 1.0 0.8 R = 10k 0.6 Cext =100 pF, T = 25C 0.4 R = 100k 0.2 0.0 2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VDD (Volts)
FIGURE 12-4: TYPICAL RC OSCILLATOR FREQUENCY vs. VDD
1.1 1.0 0.9 0.8 Cext = 300 pF, T = 25C 0.7 FOSC (MHz) R = 3.3k 0.6 0.5 R = 5k 0.4 0.3 0.2 0.1 R = 100k 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 R = 10k
VDD (Volts)
(c) 1995 Microchip Technology Inc.
DS30081F-page 83
PIC16C8X
Applicable Devices 83 R83 84 84A R84 FIGURE 12-5: TYPICAL IPD vs. VDD WATCHDOG DISABLED (25C)
60
50
40 IPD (A)
30
20
10
0 2.0 2.5 3.0 3.5 4.0 VDD (Volts) 4.5 5.0 5.5 6.0
FIGURE 12-6: TYPICAL IPD vs. VDD WATCHDOG ENABLED (25C)
60
50
40 IPD(A)
30
20
10
0 2.0 2.5 3.0 3.5 4.0 VDD (Volts) 4.5 5.0 5.5 6.0
DS30081F-page 84
(c) 1995 Microchip Technology Inc.
PIC16C8X
Applicable Devices 83 R83 84 84A R84 FIGURE 12-7: MAXIMUM IPD vs. VDD WATCHDOG DISABLED
120
100
em Max. T 5C p. = 8
80 IPD(A)
60
5C p. = 2 p. Tem Ty em Min. T 0C p. = -4
40
20
0 2.0 2.5 3.0 3.5 4.0 VDD (Volts) 4.5 5.0 5.5 6.0
FIGURE 12-8: MAXIMUM IPD vs. VDD WATCHDOG ENABLED*
120
100
emp. Max. T e Typ. T = 85C 25C
80 IPD(A)
mp. =
60
C . = -40 . Temp Min
40
20
0 2.0 2.5 3.0 3.5 4.0 VDD (Volts) * IPD, with Watchdog Timer enabled, has two components: The leakage current which increases with higher temperature and the operating current of the Watchdog Timer logic which increases with lower temperature. At -40C, the latter dominates explaining the apparently anomalous behavior. 4.5 5.0 5.5 6.0
(c) 1995 Microchip Technology Inc.
DS30081F-page 85
PIC16C8X
Applicable Devices 83 R83 84 84A R84 FIGURE 12-9: VTH (INPUT THRESHOLD VOLTAGE) OF I/O PINS vs. VDD
2.0 1.8 Max (-40C to +85C) 1.6 VTH(Volts) Typ @ 25C 1.4 1.2 1.0 0.8 0.6 2.5 Min (-40C to +85C)
3.0
3.5
4.0 VDD (Volts)
4.5
5.0
5.5
6.0
FIGURE 12-10: VTH (INPUT THRESHOLD VOLTAGE) OF OSC1 INPUT (IN XT, HS, AND LP MODES) vs. VDD
3.4 3.2 3.0 2.8 VTH (Volts) 2.6 2.4 2.2 2.0 1.8 1.6 1.4 1.2 1.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
M (ax C 40 C) +85 to
Typ
C) (25
( Min
C -40
C) +85 to
VDD (Volts)
DS30081F-page 86
(c) 1995 Microchip Technology Inc.
PIC16C8X
Applicable Devices 83 R83 84 84A R84 FIGURE 12-11: VIH, VIL OF MCLR, T0CKI and OSC1 (IN RC MODE) vs. VDD
5.0 VIH, max (-40C to +85C) 4.5 VIH, typ (25C) 4.0 VIH, min (-40C to +85C) 3.5 VIH, VIL(volts) 3.0 2.5 2.0 1.5 1.0 0.5 0.0 2.0 2.5 3.0 3.5 4.0 VDD (Volts) 4.5 5.0 5.5 6.0 VIL, max (-40C to +85C) VIL, typ (25C) VIL, min (-40C to +85C)
(c) 1995 Microchip Technology Inc.
DS30081F-page 87
PIC16C8X
Applicable Devices 83 R83 84 84A R84 FIGURE 12-12: TYPICAL IDD vs. FREQ (EXT CLOCK, 25C)
10,000
1,000
IDD (A) 100
6.0V 5.5V 5.0V 4.5V 4.0V 3.5V 3.0V 2.5V 2.0V
10 10k 100k 1M External Clock Frequency (Hz) 10M 100M
FIGURE 12-13: MAXIMUM IDD vs. FREQ (EXT CLOCK, -40 TO +85C)
10,000
1,000
IDD (A)
100
6.0V 5.5V 5.0V 4.5V 4.0V 3.5V 3.0V 2.5V 2.0V
10 10k 100k 1M External Clock Frequency (Hz) 10M 100M
DS30081F-page 88
(c) 1995 Microchip Technology Inc.
PIC16C8X
Applicable Devices 83 R83 84 84A R84 FIGURE 12-14: WDT TIMER TIME-OUT PERIOD vs. VDD
70
60 Max. 85C WDT Period (ms) 50 Max. 70C 40 Typ. 25C 30 Min. 0C 20 Min. -40C 10
0 2.0 2.5 3.0 3.5 4.0 VDD (Volts) 4.5 5.0 5.5 6.0
FIGURE 12-15: TRANSCONDUCTANCE (gm) OF HS OSCILLATOR vs. VDD
10000 9000 8000 7000 6000 gm(A/V) 5000 Max @ -40C 4000 3000 Min @ 85C 2000 1000 0 2.0 3.5 3.0 3.5 VDD (Volts) 4.0 4.5 5.0 5.5 Typ @ 25C
(c) 1995 Microchip Technology Inc.
DS30081F-page 89
PIC16C8X
Applicable Devices 83 R83 84 84A R84 FIGURE 12-16: TRANSCONDUCTANCE (gm) OF LP OSCILLATOR vs. VDD
250 225 200 175 Max @ -40C 150 gm(A/V) 125 100 75 50 25 0 2.0 2.5 3.0 3.5 VDD (Volts) 4.0 4.5 5.0 5.5 Min @ 85C Typ @ 25C
FIGURE 12-17: TRANSCONDUCTANCE (gm) OF XT OSCILLATOR vs. VDD
2000 1800 1600 1400 1200 gm(A/V) 1000 800 600 400 200 0 2.0 2.5 3.0 3.5 VDD (Volts) 4.0 4.5 5.0 5.5 Min @ 85C Max @ -40C Typ @ 25C
DS30081F-page 90
(c) 1995 Microchip Technology Inc.
PIC16C8X
Applicable Devices 83 R83 84 84A R84 FIGURE 12-18: IOH vs. VOH, VDD = 3V
0 -2 -4 IOH (mA) -6 -8 -10 -12 -14 -16 -18 0.0 0.5 1.0 1.5 VDD (Volts) 2.0 2.5 3.0 Max @ -40C Typ @ 25C Min @ 85C
FIGURE 12-19: IOH vs. VOH, VDD = 5V
0 -5 -10 Min @ 85C -15 -20 Max @ -40C IOH (mA) -25 -30 -35 -40 -45 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 Typ @ 25C
VDD (Volts)
(c) 1995 Microchip Technology Inc.
DS30081F-page 91
PIC16C8X
Applicable Devices 83 R83 84 84A R84 FIGURE 12-20: IOL vs. VOL, VDD = 3V
35 Max. -40C 30 Typ. 25C 25 IOL (mA)
20 Min. +85C 15
10
5
0 0.0 0.5 1.0 1.5 VDD (Volts) 2.0 2.5 3.0
FIGURE 12-21: IOL vs. VOL, VDD = 5V
90 80 Max @ -40C 70 IOL (mA) 60 50 40 Min @ +85C 30 20 10 0 0.0 0.5 1.0 1.5 VDD (Volts) 2.0 2.5 3.0 Typ @ 25C
DS30081F-page 92
(c) 1995 Microchip Technology Inc.
PIC16C8X
Applicable Devices 83 R83 84 84A R84 TABLE 12-2: INPUT CAPACITANCE *
Typical Capacitance (pF) Pin Name 18L PDIP PORTA PORTB MCLR OSC1/CLKIN OSC2/CLKOUT T0CKI 5.0 5.0 17.0 4.0 4.3 3.2 18L SOIC 4.3 4.3 17.0 3.5 3.5 2.8
* All capacitance values are typical at 25C. A part to part variation of 25% (three standard deviations) should be taken into account.
(c) 1995 Microchip Technology Inc.
DS30081F-page 93
PIC16C8X
Applicable Devices 83 R83 84 84A R84 NOTES:
DS30081F-page 94
(c) 1995 Microchip Technology Inc.
PIC16C8X
Applicable Devices 83 R83 84 84A R84
13.0
ELECTRICAL CHARACTERISTICS FOR PIC16C83, PIC16CR83, PIC16C84A AND PIC16CR84
Absolute Maximum Ratings Ambient temperature under bias.............................................................................................................-55C to +125C Storage temperature .............................................................................................................................. -65C to +150C Voltage on any pin with respect to VSS (except VDD and MCLR).................................................... -0.6V to (VDD + 0.6V) Voltage on VDD with respect to VSS ............................................................................................................... 0 to +7.5V Voltage on MCLR with respect to VSS (Note 2).................................................................................................0 to +14V Total power dissipation (Note 1)...........................................................................................................................800 mW Maximum current out of VSS pin ...........................................................................................................................150 mA Maximum current into VDD pin ..............................................................................................................................100 mA Input clamp current, IIK (VI < 0 or VI > VDD) ..................................................................................................................... 20 mA Output clamp current, IOK (V0 < 0 or V0 > VDD) .............................................................................................................. 20 mA Maximum output current sunk by any I/O pin..........................................................................................................25 mA Maximum output current sourced by any I/O pin ....................................................................................................20 mA Maximum current sunk by PORTA ..........................................................................................................................80 mA Maximum current sourced by PORTA .....................................................................................................................50 mA Maximum current sunk by PORTB........................................................................................................................150 mA Maximum current sourced by PORTB...................................................................................................................100 mA Note 1: Power dissipation is calculated as follows: Pdis = VDD x {IDD - IOH} + {(VDD-VOH) x IOH} + (VOl x IOL) Note 2: Voltage spikes below VSS at the MCLR pin, inducing currents greater than 80 mA, may cause latch-up. Thus, a series resistor of 50-100 should be used when applying a "low" level to the MCLR pin rather than pulling this pin directly to VSS. NOTICE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.
(c) 1995 Microchip Technology Inc.
Preliminary
Thi d t t d ith F Mk 404
DS30081F-page 95
PIC16C8X
Applicable Devices 83 R83 84 84A R84 TABLE 13-1: CROSS REFERENCE OF DEVICE SPECS FOR OSCILLATOR CONFIGURATIONS AND FREQUENCIES OF OPERATION (COMMERCIAL DEVICES)
PIC16C84A-04 PIC16CR84-04 PIC16C83-04 PIC16CR83-04
VDD: IDD: IPD: Freq: VDD: IDD: IPD: Freq: VDD: IDD: IPD: Freq: VDD: IDD: IPD: Freq: 4.0V to 6.0V 4.5 mA max. at 5.5V 14 A max. at 4V WDT dis 4.0 MHz max. 4.0V to 6.0V 4.5 mA max. at 5.5V 14 A max. at 4V WDT dis 4.0 MHz max. 4.5V to 5.5V 4.5 mA typ. at 5.5V 1.0 A typ. at 4.5V WDT dis 4.0 MHz max. 4.0V to 6.0V 35 A typ. at 32 kHz, 3.0V 0.6 A typ. at 3.0V WDT dis 200 kHz max. VDD: IDD: IPD: Freq: VDD: IDD: IPD: Freq: VDD:
OSC
PIC16C84A-10 PIC16CR84-10 PIC16C83-10 PIC16CR83-10
4.5V to 5.5V 1.8 mA typ. at 5.5V 1.0 A typ. at 5.5V WDT dis 4..0 MHz max. 4.5V to 5.5V 1.8 mA typ. at 5.5V 1.0 A typ. at 5.5V WDT dis 4.0 MHz max. 4.5V to 5.5V VDD: IDD: IPD: Freq:
PIC16LC84A-04 PIC16LCR84-94 PIC16LC83-04 PIC16LCR83-04
2.0V to 6.0V 4.5 mA max. at 5.5V 7.0 A max. at 2V WDT dis 2.0 MHz max.
RC
XT
HS
VDD: 2.0V to 6.0V IDD: 4.5 mA max. at 5.5V IPD: 7.0 A max. at 2V WDT dis Freq: 2.0 MHz max. Do not use in HS mode
IDD: 10 mA max. at 5.5V typ. IPD: 1.0 A typ. at 4.5V WDT dis Freq: 10 MHz max. Do not use in LP mode
LP
VDD: IDD: IPD: Freq:
2.0V to 6.0V 32 A max. at 32 kHz, 3.0V 7 A max. at 2.0V WDT dis 200 kHz max.
The shaded sections indicate oscillator selections which are tested for functionality, but not for MIN/MAX specifications. It is recommended that the user select the device type that ensures the specifications required.
DS30081F-page 96
Preliminary
(c) 1995 Microchip Technology Inc.
PIC16C8X
Applicable Devices 83 R83 84 84A R84 13.1 DC CHARACTERISTICS: PIC16C84A, PIC16C83 (Commercial, Industrial) PIC16CR84, PIC16CR83 (Commercial, Industrial)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial and 0C TA +70C for commercial Min Typ Max Units Conditions 4.0 4.5 1.5 *
-- -- -- --
DC CHARACTERISTICS
Parameter No.
Sym VDD VDR VPOR
Characteristic Supply Voltage RAM Data Retention Voltage (Note 1) VDD start voltage to ensure Power-on Reset VDD rise rate to ensure Power-on Reset Supply Current (Note 2)
D001 D001A D002 D003
6.0 5.5
-- --
V V V V
XT, RC and LP osc configuration HS osc configuration Device in SLEEP mode See section on Power-on Reset for details
VSS
D004
SVDD
0.05*
--
--
V/ms See section on Power-on Reset for details
IDD D010 D010A
-- --
1.8 7.3
4.5 10
mA mA
-- D013 5 10 mA D020 IPD Power-down Current -- 7.0 28 A D021 (Note 3) 1.0 14 A -- D021A 1.0 16 A -- * These parameters are characterized but not tested. Data in "Typ" column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1=external square wave, from rail to rail; all I/O pins tristated, pulled to VDD, T0CKI = VDD, MCLR = VDD; WDT enabled/disabled as specified. 3: The power down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS. 4: For RC osc configuration, current through Rext is not included. The current through the resistor can be estimated by the formula IR = VDD/2Rext (mA) with Rext in kOhm.
RC and XT osc configuration (Note 4) FOSC = 4.0 MHz, VDD = 5.5V FOSC = 4.0 MHz, VDD = 5.5V (During EEPROM programming) HS OSC CONFIGURATION (PIC16C84-10) FOSC = 10 MHz, VDD = 5.5V VDD = 4.0V, WDT enabled, -40C to +85C VDD = 4.0V, WDT disabled, -0C to +70C VDD = 4.0V, WDT disabled, -40C to +85C
(c) 1995 Microchip Technology Inc.
Preliminary
DS30081F-page 97
PIC16C8X
Applicable Devices 83 R83 84 84A R84 13.2 DC CHARACTERISTICS: PIC16LC84A, PIC16LC83 (Commercial, Industrial) PIC16LCR84, PIC16LCR83 (Commercial, Industrial)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial and 0C TA +70C for commercial Min Typ Max Units Conditions 2.0 1.5 * -- -- -- VSS 6.0 -- -- V V V XT, RC, and LP osc configuration Device in SLEEP mode See section on Power-on Reset for details
DC CHARACTERISTICS
Parameter No.
Sym VDD VDR VPOR
Characteristic Supply Voltage RAM Data Retention Voltage (Note 1) VDD start voltage to ensure Power-on Reset VDD rise rate to ensure Power-on Reset Supply Current (Note 2)
D001 D002 D003
D004
SVDD
0.05*
--
--
V/ms See section on Power-on Reset for details
IDD D010 D010A
-- --
1.8 7.3
4.5 10
mA mA A
D014
--
15
32
IPD D020 Power-down Current -- 3.0 16 A D021 (Note 3) -- 0.4 7.0 A D021A -- 0.4 9.0 A * These parameters are characterized but not tested. Data in "Typ" column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1=external square wave, from rail to rail; all I/O pins tristated, pulled to VDD, T0CKI = VDD, MCLR = VDD; WDT enabled/disabled as specified. 3: The power down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS. 4: For RC osc configuration, current through Rext is not included. The current through the resistor can be estimated by the formula IR = VDD/2Rext (mA) with Rext in kOhm.
RC and XT osc configuration (Note 4) FOSC = 2.0 MHz, VDD = 5.5V FOSC = 2.0 MHz, VDD = 5.5V (During EEPROM programming) LP osc configuration FOSC = 32 kHz, VDD = 2.0V, WDT disabled VDD = 2.0V, WDT enabled, -40C to +85C VDD = 2.0V, WDT disabled, 0C to +70C VDD = 2.0V, WDT disabled, -40C to +85C
DS30081F-page 98
Preliminary
(c) 1995 Microchip Technology Inc.
PIC16C8X
Applicable Devices 83 R83 84 84A R84 13.3 DC CHARACTERISTICS: PIC16C84A, PIC16C83 (Commercial, Industrial) PIC16CR84A, PIC16CR83 (Commercial, Industrial) PIC16LC84A, PIC16LC83 (Commercial, Industrial) PIC16LCR84, PIC16LCR83 (Commercial, Industrial)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial and 0C TA +70C for commercial Operating voltage VDD range as described in DC spec Section 13-1 and Section 13-3 Characteristic Input Low Voltage I/O ports with TTL buffer with Schmitt Trigger buffer MCLR, RA4/T0CKI OSC1 (XT, HS and LP modes) OSC1 (RC mode) Input High Voltage I/O ports with TTL buffer Min Typ Max Units Conditions
DC CHARACTERISTICS
Parameter No.
Sym VIL
D030 D030A D031 D032 D033 D034 VIH D040 D040A D041 D042 D043 D050 D070
VSS VSS VSS Vss Vss Vss
-- -- -- -- -- -- --
0.8 0.16VDD 0.2VDD 0.2VDD 0.3VDD 0.1VDD
V V V V V V
4.5 V Vdd 5.5 V entire range (Note 4) entire range Note1
VHYS IPURB
D060 D061 D063
IIL
-- 2.4 -- 0.48VDD with Schmitt Trigger buffer 0.45VDD -- MCLR, RA4/T0CKI, OSC1 0.85 VDD -- (RC mode) -- OSC1 (XT, HS and LP modes) 0.7 VDD Hysteresis of TBD -- Schmitt Trigger inputs PORTB weak pull-up current 50* 250* Input Leakage Current (Notes 2, 3) I/O ports -- --
VDD VDD VDD VDD VDD
--
V V V V V
4.5 V VDD 5.5V entire range (Note 4) entire range
Note1
400*
A VDD = 5.0V, VPIN = VSS
1 5 5
MCLR, RA4/T0CKI OSC1
-- --
-- --
A Vss VPIN VDD, Pin at hi-impedance A Vss VPIN VDD A Vss VPIN VDD, XT, HS and LP osc configuration
Output Low Voltage I/O ports -- -- 0.6 V IOL = 8.5 mA, VDD = 4.5V OSC2/CLKOUT -- -- 0.6 V IOL = 1.6 mA, VDD = 4.5V Output High Voltage D090 VOH I/O ports (Note 3) VDD-0.7 -- -- V IOH = -3.0 mA, VDD = 4.5V D092 OSC2/CLKOUT VDD-0.7 -- -- V IOH = -1.3 mA, VDD = 4.5V * These parameters are characterized but not tested. Data in "Typ" column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: In RC oscillator configuration, the OSC1 pin is a Schmitt Trigger input. Do not drive the PIC16C8X with an external clock while the device is in RC mode, otherwise chip damage may result. 2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 3: Negative current is defined as coming out of the pin. 4: The user may use better of the two specs. D080 D083 VOL
(c) 1995 Microchip Technology Inc.
Preliminary
DS30081F-page 99
PIC16C8X
Applicable Devices 83 R83 84 84A R84 13.4 DC CHARACTERISTICS: PIC16C84A, PIC16C83 (Commercial, Industrial) PIC16CR84A, PIC16CR83 (Commercial, Industrial) PIC16LC84A, PIC16C83 (Commercial, Industrial) PIC16LCR84A, PIC16LCR83 (Commercial, Industrial)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial and 0C TA +70C for commercial Operating voltage VDD range as described in DC spec Section 13-1 and Section 13-3 Min Typ Max Units Conditions
DC CHARACTERISTICS
Parameter No.
Sym
Characteristic
D100
Capacitive Loading Specs on Output Pins COSC2 OSC2 pin
--
--
15
pF
In XT, HS and LP modes when external clock is used to drive OSC1.
D101
CIO
All I/O pins and OSC2 (RC mode) Data EEPROM Memory Endurance VDD for read/write Erase/Write cycle time Program EEPROM Memory Endurance VDD for read
--
--
50
pF
D120 D121 D122 D130 D131
ED VDRW TDEW EP VPR
100,000 1,000,000 VMIN --
-- --
--
6.0 10
--
E/W V VMIN = Minimum operating voltage ms
E/W V VMIN = Minimum operating voltage D132 VPEW VDD for erase/write 4.5 -- 5.5 V D133 TPEW Erase/Write cycle time -- 10 -- ms Data in "Typ" column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested.
--
100 VMIN
1000
6.0
DS30081F-page 100
Preliminary
(c) 1995 Microchip Technology Inc.
PIC16C8X
Applicable Devices 83 R83 84 84A R84 TABLE 13-2: TIMING PARAMETER SYMBOLOGY
The timing parameter symbols have been created following one of the following formats: 1. TppS2ppS 2. TppS T F Frequency Lowercase symbols (pp) and their meanings: pp ck CLKOUT io I/O port mc MCLR Uppercase symbols and their meanings: S F Fall H High I Invalid (Hi-impedance) L Low
T
Time
osc t0
OSC1 T0CKI
P R V Z
Period Rise Valid High Impedance
FIGURE 13-1: PARAMETER MEASUREMENT INFORMATION
All timings are measure between high and low measurement points as indicated in the figures below.
0.7 VDD XTAL 0.8 VDD RC (High) 0.3 VDD XTAL 0.15 VDD RC (Low) OSC1 Measurement Points I/O Port Measurement Points
0.9 VDD (High) 0.1 VDD (Low)
FIGURE 13-2: LOAD CONDITIONS
Load Condition 1 VDD/2 RL Pin VSS RL = CL = 464 50 pF 15 pF for all pins except OSC2. for OSC2 output. CL Pin VSS CL Load Condition 2
(c) 1995 Microchip Technology Inc.
Preliminary
DS30081F-page 101
PIC16C8X
Applicable Devices 83 R83 84 84A R84 13.5 Timing Diagrams and Specifications for PIC16C83, PIC16CR83, PIC16C84A, and PIC16CR84
FIGURE 13-3: EXTERNAL CLOCK TIMING
Q4 OSC1 1 2 CLKOUT 3 3 4 4 Q1 Q2 Q3 Q4 Q1
TABLE 13-3:
Parameter No.
EXTERNAL CLOCK TIMING REQUIREMENTS
Sym Fos Characteristic External CLKIN Frequency (Note 1) Min DC DC DC DC Oscillator Frequency (Note 1) DC DC 0.1 0.1 1.0 DC Typ -- -- -- -- -- -- -- -- -- -- Max 2 4 10 200 2 4 2 4 10 200 Units Conditions MHz MHz MHz kHz MHz MHz MHz MHz MHz kHz XT, RC osc XT, RC osc HS osc LP osc RC osc RC osc XT osc XT osc HS osc LP osc PIC16LC8X-04 PIC16LCR8X-04 PIC16C8X-04 PIC16CR8X-04 PIC16C8X-10 PIC16CR8X-10 PIC16LC8X-04 PIC16LCR8X-04 PIC16LC8X-04 PIC16LCR8X-04 PIC16C8X-04 PIC16CR8X-04 PIC16LC8X-04 PIC16LCR8X-04 PIC16C8X-04 PIC16CR8X-04 PIC16C8X-10 PIC16CR8X-10 PIC16LC8X-04 PIC16LCR8X-04
Data in "Typ" column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at "min." values with an external clock applied to the OSC1 pin. When an external clock input is used, the "Max." cycle time limit is "DC" (no clock) for all devices.
DS30081F-page 102
Preliminary
(c) 1995 Microchip Technology Inc.
PIC16C8X
Applicable Devices 83 R83 84 84A R84 TABLE 13-3:
Parameter No. 1
EXTERNAL CLOCK TIMING REQUIREMENTS (CONTINUED)
Sym TOSC Characteristic External CLKIN Period (Note 1) Min 500 250 100 5.0 Oscillator Period (Note 1) 500 250 500 250 100 5.0 Typ -- -- -- -- -- -- -- -- -- -- 4/Fosc -- -- -- -- -- -- -- Max -- -- -- -- -- -- 10,000 10,000 1,000 -- DC -- -- -- -- -- -- -- Units Conditions ns ns ns s ns ns ns ns ns s s ns ns s ns ns ns ns XT, RC osc XT, RC osc HS osc LP osc RC osc RC osc XT osc XT osc HS osc LP osc PIC16LC8X-04 PIC16LCR8X-04 PIC16C8X-04 PIC16CR8X-04 PIC16C8X-10 PIC16CR8X-10 PIC16LC8X-04 PIC16LCR8X-04 PIC16LC8X-04 PIC16LCR8X-04 PIC16C8X-04 PIC16CR8X-04 PIC16LC8X-04 PIC16LCR8X-04 PIC16C8X-04 PIC16CR8X-04 PIC16C8X-10 PIC16CR8X-10 PIC16LC8X-04 PIC16LCR8X-04 PIC16LC8X-04 PIC16LCR8X-04 PIC16C8X-04 PIC16CR8X-04 PIC16LC8X-04 PIC16LCR8X-04 PIC16C8X-10 PIC16CR8X-10 PIC16C8X-04 PIC16CR8X-04 PIC16LC8X-04 PIC16LCR8X-04 PIC16C8X-10 PIC16CR8X-10
2 3
TCY TosL, TosH
Instruction Cycle Time (Note 1) Clock in (OSC1) High or Low Time
0.4 60 * 50 * 2.0 * 35 *
XT osc XT osc LP osc HS osc XT osc LP osc HS osc
4
TosR, TosF
Clock in (OSC1) Rise or Fall Time
25 * 50 * 15 *
Data in "Typ" column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at "min." values with an external clock applied to the OSC1 pin. When an external clock input is used, the "Max." cycle time limit is "DC" (no clock) for all devices.
(c) 1995 Microchip Technology Inc.
Preliminary
DS30081F-page 103
PIC16C8X
Applicable Devices 83 R83 84 84A R84 FIGURE 13-4: CLKOUT AND I/O TIMING
Q4 OSC1 10 CLKOUT 13 14 I/O Pin (input) 17 I/O Pin (output) old value 20, 21 Note: All tests must be done with specified capacitive loads (Figure 13-2) 50 pF on I/O pins and CLKOUT. 15 new value 19 22 23 12 18 16 Q1 Q2 11 Q3
TABLE 13-4:
Parameter No. 10 10A 11 11A 12 12A 13 13A 14 15 16 17 18 19 20 20A 21 21A 22 22A 23 23A
CLKOUT AND I/O TIMING REQUIREMENTS
Sym TosH2ckL Characteristic OSC1 to CLKOUT PIC16C8X PIC16LC8X TosH2ckH TckR TckF TckL2ioV TioV2ckH TckH2ioI TosH2ioV TosH2ioI TioV2osH TioR TioF Tinp Trbp OSC1 to CLKOUT CLKOUT rise time CLKOUT fall time PIC16C8X PIC16LC8X PIC16C8X PIC16LC8X PIC16C8X PIC16LC8X CLKOUT to Port out valid Port in valid before CLKOUT OSC1 (Q1 cycle) to Port out valid PIC16C8X PIC16LC8X PIC16C8X PIC16LC8X Min -- -- -- -- -- -- -- -- -- 0.30TCY + 30 * 0.30TCY + 80 * 0* -- -- TBD TBD -- -- -- -- 20 * 55 * TOSC TOSC Typ 15 15 15 15 15 15 15 15 -- -- -- -- -- -- -- -- 10 10 10 10 -- -- -- -- Max 30 * 120 * 30 * 120 * 30 * 100 * 30 * 100 * 0.5TCY +20 * -- -- -- 125 * 250 * -- -- 25 * 60 * 25 * 60 * -- -- -- -- Units Conditions ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Note 1 Note 1 Note 1 Note 1 Note 1 Note 1 Note 1 Note 1 Note 1 Note 1 Note 1 Note 1
Port in hold after CLKOUT
OSC1 (Q2 cycle) to Port input invalid (I/O in hold time) Port input valid to OSC1 (I/O in setup time) Port output rise time Port output fall time INT pin high or low time RB7:RB4 change INT high or low time PIC16C8X PIC16LC8X PIC16C8X PIC16LC8X PIC16C8X PIC16LC8X PIC16C8X PIC16LC8X
These parameters are characterized but not tested. Data in "Typ" column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. By design Note 1: Measurements are taken in RC Mode where CLKOUT output is 4 x TOSC.
*
DS30081F-page 104
Preliminary
(c) 1995 Microchip Technology Inc.
PIC16C8X
Applicable Devices 83 R83 84 84A R84 FIGURE 13-5: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING
VDD MCLR 30 Internal POR 33 PWRT Time-out OSC Time-out Internal RESET Watchdog Timer RESET 34 I/O Pins 32
31 34
TABLE 13-5:
Parameter No. 30 31 32 33 34 *
RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER REQUIREMENTS
Sym TmcL Twdt Tost Tpwrt TIOZ Characteristic MCLR Pulse Width (low) Watchdog Timer Time-out Period (No Prescaler) Oscillation Start-up Timer Period Power-up Timer Period I/O Hi-impedance from MCLR Low or reset 28 * -- Min 1000 * 7* Typ -- 18 1024TOSC 72 -- 132 * 100 * Max -- 33 * Units ns ms ms ms ns Conditions 2.0V VDD 6.0V
VDD = 5.0V
TOSC = OSC1 period
VDD = 5.0V
These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested.
(c) 1995 Microchip Technology Inc.
Preliminary
DS30081F-page 105
PIC16C8X
Applicable Devices 83 R83 84 84A R84 FIGURE 13-6: TIMER0 CLOCK TIMINGS
RA4/T0CKI
40
41
42
TABLE 13-6:
Parameter No. 40
TIMER0 CLOCK REQUIREMENTS
Min No Prescaler With Prescaler 0.5TCY + 20 * 50 * 30 * 0.5TCY + 20 * 50 * 20 * TCY + 40 * N Typ Max Units Conditions -- -- -- -- -- -- -- -- -- -- -- -- -- -- ns ns ns ns ns ns ns 2.0V VDD 3.0V 3.0V VDD 6.0V N = prescale value (2, 4, ..., 256) 2.0V VDD 3.0V 3.0V VDD 6.0V
Sym Characteristic Tt0H T0CKI High Pulse Width
41
Tt0L T0CKI Low Pulse Width
No Prescaler With Prescaler
42 *
Tt0P T0CKI Period
These parameters are characterized but not tested. Data in "Typ" column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested.
DS30081F-page 106
Preliminary
(c) 1995 Microchip Technology Inc.
PIC16C8X
Applicable Devices 83 R83 84 84A R84
14.0
DC & AC CHARACTERISTICS GRAPHS/TABLES FOR PIC16C83, PIC16CR83, PIC16C84A, AND PIC16CR84
Device Characteristics Not Available at This Time
(c) 1995 Microchip Technology Inc.
DS30081F-page 107
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PIC16C8X
Applicable Devices 83 R83 84 84A R84 TABLE 14-1: INPUT CAPACITANCE *
Typical Capacitance (pF) Pin Name 18L PDIP PORTA PORTB MCLR OSC1/CLKIN OSC2/CLKOUT T0CKI 5.0 5.0 17.0 4.0 4.3 3.2 18L SOIC 4.3 4.3 17.0 3.5 3.5 2.8
* All capacitance values are typical at 25C. A part to part variation of 25% (three standard deviations) should be taken into account.
DS30081F-page 108
(c) 1995 Microchip Technology Inc.
PIC16C8X
15.0
15.1
PACKAGING INFORMATION
18-Lead Plastic Dual In-line (300 mil)
N E1 E Pin No. 1 Indicator Area eA eB C
D S Base Plane Seating Plane B1 B D1 e1 L A1 A2 A S1
Package Group: Plastic Dual In-Line (PLA) Millimeters Symbol A A1 A2 B B1 C D D1 E E1 e1 eA eB L N S S1 Min 0 - 0.381 3.048 0.355 1.524 0.203 22.479 20.320 7.620 6.096 2.489 7.620 7.874 3.048 18 0.889 0.127 Max 10 4.064 - 3.810 0.559 1.524 0.381 23.495 20.320 8.255 7.112 2.591 7.620 9.906 3.556 18 - - Notes Min 0 - 0.015 0.120 0.014 0.060 0.008 0.885 0.800 0.300 0.240 0.098 0.300 0.310 0.120 18 0.035 0.005 Inches Max 10 0.160 - 0.150 0.022 0.060 0.015 0.925 0.800 0.325 0.280 0.102 0.300 0.390 0.140 18 - - Notes
Reference Typical Reference
Reference Typical Reference
Typical Reference
Typical Reference
(c) 1995 Microchip Technology Inc.
DS30081F-page 109
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PIC16C8X
15.2 18-Lead Plastic Surface Mount (SOIC - Wide, 300 mil Body)
e B N Index Area E Chamfer h x 45 1 2 3 H L C h x 45
D
Seating Plane
CP
Base Plane
A1
A
Package Group: Plastic SOIC (SO) Millimeters Symbol A A1 B C D E e H h L N CP Min 0 2.362 0.101 0.355 0.241 11.353 7.416 1.270 10.007 0.381 0.406 18 - Max 8 2.642 0.300 0.483 0.318 11.735 7.595 1.270 10.643 0.762 1.143 18 0.102 Notes Min 0 0.093 0.004 0.014 0.009 0.447 0.292 0.050 0.394 0.015 0.016 18 - Inches Max 8 0.104 0.012 0.019 0.013 0.462 0.299 0.050 0.419 0.030 0.045 18 0.004 Notes
Reference
Reference
DS30081F-page 110
(c) 1995 Microchip Technology Inc.
PIC16C8X
15.3 Package Marking Information
18L PDIP
MMMMMMMMMMMMXXX MMMMMMMMXXXXXXXX AABB CDE
Example
PIC16C84 10I/P 9305 CBA
18L SOIC
XXXXXXXX XXXXXXXX
Example
PIC16LC84 04I/S0218
AABB CDE
9310 CBA
Microchip part number information Customer specific information* Year code (last two digits of calendar year) Week code (week of January 1 is week `01') Facility code of the plant at which wafer is manufactured C = Chandler, Arizona, U.S.A., S = Tempe, Arizona, U.S.A. D Mask revision number E Assembly code of the plant or country of origin in which part was assembled Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line thus limiting the number of available characters for customer specific information. * Standard OTP marking consists of Microchip part number, year code, week code, facility code, mask rev#, and assembly code. For OTP marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price.
Legend: MM...M XX...X AA BB C
(c) 1995 Microchip Technology Inc.
DS30081F-page 111
PIC16C8X
NOTES:
DS30081F-page 112
(c) 1995 Microchip Technology Inc.
PIC16C8X
APPENDIX A: CHANGES
The following is the list of modifications over the PIC16C5X microcontroller family: 1. Instruction word length is increased to 14 bits. This allows larger page sizes both in program memory (2K now as opposed to 512 before) and the register file (128 bytes now versus 32 bytes before). A PC latch register (PCLATH) is added to handle program memory paging. PA2, PA1 and PA0 bits are removed from the status register and placed in the option register. Data memory paging is redefined slightly. The STATUS register is modified. Four new instructions have been added: RETURN, RETFIE, ADDLW, and SUBLW. Two instructions, TRIS and OPTION, are being phased out although they are kept for compatibility with PIC16C5X. OPTION and TRIS registers are made addressable. Interrupt capability is added. Interrupt vector is at 0004h. Stack size is increased to 8 deep. Reset vector is changed to 0000h. Reset of all registers is revisited. Five different reset (and wake-up) types are recognized. Registers are reset differently. Wake up from SLEEP through interrupt is added. Two separate timers, the Oscillator Start-up Timer (OST) and Power-up Timer (PWRT), are included for more reliable power-up. These timers are invoked selectively to avoid unnecessary delays on power-up and wake-up. PORTB has weak pull-ups and interrupt on change features. T0CKI pin is also a port pin (RA4/T0CKI). FSR is a full 8-bit register. "In system programming" is made possible. The user can program PIC16CXX devices using only five pins: VDD, VSS, VPP, RB6 (clock) and RB7 (data in/out).
APPENDIX B: COMPATIBILITY
To convert code written for PIC16C5X to PIC16C8X, the user should take the following steps: 1. 2. Remove any program memory page select operations (PA2, PA1, PA0 bits) for CALL, GOTO. Revisit any computed jump operations (write to PC or add to PC, etc.) to make sure page bits are set properly under the new scheme. Eliminate any data memory page switching. Redefine data variables for reallocation. Verify all writes to STATUS, OPTION, and FSR registers since these have changed. Change reset vector to 0000h.
2.
3. 4. 5.
3. 4.
5. 6. 7. 8. 9.
10. 11.
12. 13. 14. 15.
(c) 1995 Microchip Technology Inc.
DS30081F-page 113
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PIC16C8X
APPENDIX C: WHAT'S NEW
Here is an overview list of new features: * Added descriptions and information for the PIC16C84A, PIC16CR84. PIC16C83 and PIC16CR83 devices.
APPENDIX D: WHAT'S CHANGED
The following lists the things that have changed: 1. Section 7.1 no longer says that the upper two bits of EEADR are not address decoded. These two bits are decoded, even when there is no data EEPROM at that location. Changed the format of the Register Definition Figures to be consistent with other new data sheets. Added parameter numbers to DC specs. Added description of MPLAB development tool software. Added new probes in Probe Specification table. Updated device family tables.
2.
3. 4. 5. 6.
DS30081F-page 114
(c) 1995 Microchip Technology Inc.
PIC16C8X
APPENDIX E: PIC16C84 CONVERSION CONSIDERATIONS
This appendix discusses some of the issues that you may encounter as you convert your design from a PIC16C84 to any of the newly introduced devices. These new devices are: * * * * 1. PIC16C83 PIC16CR83 PIC16C84A PIC16CR84 The polarity of the PWRTE configuration bit has been reversed. Ensure that the programmer has this bit correctly set before programming. The PIC16C84A and PIC16CR84 have larger RAM sizes. Ensure that this does not cause an issue with your program. The MCLR pin now has an on-chip filter. The input signal on the MCLR pin will require a longer low pulse to generate an interrupt. Many electrical specifications have been improved. Compare the electrical specifications of the two devices to ensure that this will not cause a compatibility issue.
Some of the issues that may be encountered are:
2.
3.
4.
(c) 1995 Microchip Technology Inc.
DS30081F-page 115
PIC16C8X
NOTES:
DS30081F-page 116
(c) 1995 Microchip Technology Inc.

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